Question

我是VHDL的新手。我目前正在研究FSM，我希望我的状态机只在我的输入发生变化时改变状态。我应该在以下代码中做出哪些更改？

entity fsm is
    Port ( clk : in STD_LOGIC;
           reset : in STD_LOGIC;
           x_in : in STD_LOGIC;                         -- input Bitstream  
           y_out : out STD_LOGIC_VECTOR (1 downto 0));  -- Encoded output
end fsm;

-----------------------------------------------------
architecture Behavioral of fsm is

  -- Building an Enumerated type for the state machine
  type state_type is (s_idle,s1,s2,s3,s4);  -- constraint length = 3, Hence number of Regs = 2 therefore Number of states = 4
  signal state, next_state: state_type ;    -- Registers to hold the Present and next states

begin
-----------------------------------------------------
  process1: process (reset, clk)             --  Sequential Logic Selection process:
     begin

          if (reset ='1') then  
              state <=s_idle;         
          elsif (clk='1' and x_in'Event) then     
              state <= next_state;  
          end if;  
-----------------------------------------------------         
  end process process1;

Answer 1

假设您想在 - ＆gt;

时进行FSM更改状态

clk很高
X_in的值更改

另外，我假设您的next_state变量是state的某个组合函数，您没有提及。只需进行一次更改即可，将X_in添加到过程敏感度列表中。

-----------------------------------------------------
  process1: process (X_in, reset, clk)             --  Sequential Logic Selection process:
     begin

          if (reset ='1') then  
              state <=s_idle;         
          elsif (clk='1' and x_in'Event) then     
              state <= next_state;  
          end if;  
-----------------------------------------------------         
  end process process1;

Answer 2

假设x_in输入同步到clk，这将按照您的描述进行：

 process1: process (reset, clk)
 begin

      if (reset ='1') then  
          state <=s_idle;         
      elsif (clk='1' and clk'Event) then
          x_in_prev <= x_in;
          if x_in_prev /= x_in then
              state <= next_state;
          end if;
      end if;
 end process process1;

您需要在架构中定义x_in_prev信号，以便进行编译。

状态转换取决于输入事件VHDL

2 个答案: