我是VHDL的新手。在我的一个任务中,我需要使用VHDL在State Table方法中实现状态机。所以我为architechture实体编写了以下代码:
X,Y是输入位,基本上这是一个moore机器,它接受两个输入并输出一位。
architecture Table of SM1_2 is
type StateTable is array(integer range<>,bit range<>,bit range<>) of integer;
type OutTable is array(integer range<>) of bit;
signal State,NextState : integer := 0;
constant ST: StateTable(0 to 3,'0' to '1','0' to '1'):=
((3,0,1,0),(2,0,1,1),(3,0,1,1),(2,0,1,0));
constant OT: OutTable(0 to 3):=
('0','1','1','0');
begin --Concurrent Statements
NextState <= ST(State,X,Y); --Next state from state table
Z <= OT(State);
ModelSim报告错误:Integer literal 3 is not of type sub-array #3 of StateTable.
我已广泛搜索,但无法为此找到解决方案。如何在VHDL中使用多维数组?
答案 0 :(得分:0)
StateTable
类型被声明为integer
类型的多维数组:
type StateTable is array(integer range<>,bit range<>,bit range<>) of integer;
从此类型创建的常量将分配一个不具有所需级别的数组:
constant ST : StateTable(0 to 3,'0' to '1','0' to '1') := ( (3,0,1,0), ...
因此尝试在常量值中添加级别,例如:
constant ST: StateTable(0 to 3,'0' to '1','0' to '1'):=
(((3, 0), (1, 0)),
((2, 0), (1, 1)),
((3, 0), (1, 1)),
((2, 0), (1, 0)));
创建常量时可以使用索引值,以便更清楚地将值分配给数组中的不同元素:
constant ST: StateTable(0 to 3,'0' to '1','0' to '1'):=
(0 => ('0' => ('0' => 3, '1' => 0),
'1' => ('0' => 1, '1' => 0)),
1 => ('0' => ('0' => 2, '1' => 0),
'1' => ('0' => 1, '1' => 1)),
2 => ('0' => ('0' => 3, '1' => 0),
'1' => ('0' => 1, '1' => 1)),
3 => ('0' => ('0' => 2, '1' => 0),
'1' => ('0' => 1, '1' => 0)));
答案 1 :(得分:0)
您还可以使用嵌套数组来构建状态表:
constant state_cnt : positive := 4;
type t_inputtable is array (bit range <>, bit range <>) of natural range 0 to state_cnt-1;
type_t_statetable is array (natural range 0 to state_cnt-1) of t_inputtable;
constant statetable is t_statetable := (
--state X, Y next state
0 => (('0', '0') => 0,
('0', '1') => 1,
('1', '0') => 2,
others => 0),
1 => (('0', '0') => 0,
('0', '1') => 3,
('1', '0') => 2,
others => 1),
-- ...
);
nextState <= statetable(State)(X, Y);
我希望在键入这一行时没有错 您还可以实现outputrecord:
type t_outputtable is record
next : natural range 0 to state_cnt-1;
O1 : bit;
O2 : bit;
end record;
type t_inputtable is array (bit range <>, bit range <>) of t_outputtable;
type_t_statetable is array (natural range 0 to state_cnt-1) of t_inputtable;
nextState <= statetable(State)(X, Y).next;
Output1 <= statetable(State)(X, Y).O1;