我需要您的帮助来计数和外部信号。基本上，我需要对一个外部信号进行计数（在我的vhdl中，我将其称为sync100k）并对其进行计数，以便为可编程的计数生成高电平有效的信号（pulse_v）。 sync100k在500 ns的时间内将保持50 ns的高电平，并在450 ns的时间内保持0的高电平，因此，如果我将count设置为1，则我希望Pulse_v在500 ns内处于高电平，因此如果我将count设置为3，则我会把pulse_v设为高1500ns。我编写了一个简单的vhdl代码，但无法正常工作。如果将注册表索引设置为1，则生成的信号不会在500ns内保持高电平，而只会保持50 ns。如果将索引设置为计数2，它将生成500ns的信号，如果将索引设置为3，则将生成550ns的信号，依此类推。也许我在我的fsm中错过了一些东西，但是我仍然不知道错误在哪里。
这是我的代码：
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
entity millipulse is
generic(N : integer := 8);
Port (
start : in STD_LOGIC := '0'; --start
pps : in STD_LOGIC :='0'; --pps
clk : in STD_LOGIC; --clock
reset : in STD_LOGIC; -- reset
sync100k : in STD_LOGIC; --100kHz sync signal
pulse: out STD_LOGIC; --pulse out
t_on: in std_logic_vector (N-1 downto 0) --count vector
);
end millipulse;
architecture behavioral of millipulse is
--type state_type is (idle, gate_up, final);
type state_type is (idle, wakeup, lighton);
signal state : state_type;
begin
process (reset, clk, start, pps, sync100k, t_on)
variable index : integer :=0;
variable pulse_v: std_logic;
variable t_onlen : integer;
begin
t_onlen := to_integer(unsigned(t_on));
if reset = '1' then
index := 0;
pulse_v := '0';
else
if rising_edge(clk) then
case state is
when idle =>
index := 0;
pulse_v :='0';
if(start = '1') then
state <= wakeup;
index := 0;
pulse_v :='0';
else
state <= idle;
end if;
when wakeup =>
if (pps='1') then
state <= lighton;
else
state <= wakeup;
end if;
when lighton =>
if (sync100k = '1') then
if index = t_onlen then
pulse_v := '0';
state <=wakeup;
else
pulse_v := '1';
index := index + 1;
state <= lighton;
end if;
end if;
when others => null;
end case;
end if;
end if;
pulse <= pulse_v;
end process;
end Behavioral;
这是我的测试台
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY millipulse_tb IS
END millipulse_tb;
ARCHITECTURE behavior OF millipulse_tb IS
signal clk : std_logic := '0';
signal reset : std_logic := '0';
signal start : std_logic := '0';
signal pps : std_logic := '0';
signal sync100k : std_logic := '0';
signal pulse : std_logic := '0'; --this is the light pulse
signal t_on : std_logic_vector(7 downto 0); --time light on
constant clk_period : time := 25 ns;
component millipulse is
port(
clk : in std_logic;
reset : in std_logic;
start : in std_logic;
pps: in std_logic;
sync100k : in std_logic;
pulse: out std_logic;
t_on: in std_logic_vector (7 downto 0)
---start : in STD_LOGIC := '0'
);
end component millipulse;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: millipulse PORT MAP (
clk => clk,
reset => reset,
start => start,
pps=> pps,
sync100k=> sync100k,
pulse => pulse,
t_on => t_on
);
-- Clock process definitions
millipulse_process :process
begin
clk <= '1';
wait for clk_period/2;
clk <= '0';
wait for clk_period/2;
end process;
stim : process
begin
t_on <= "00000011";
wait for 100 ns;
reset <='1';
wait for 100 ns;
reset <='0';
wait for 100 ns;
start <= '1';
wait for 100 ns;
start <='0';
wait for 1 ns;
wait for 100 ns;
pps <='1';
wait for 100 ns;
pps <='0';
wait for 200 ns;
sync100k <= '1';
wait for 50 ns;
sync100k <= '0';
wait for 450 ns;
sync100k <= '1';
wait for 50 ns;
sync100k <= '0';
wait for 450 ns;
sync100k <= '1';
wait for 50 ns;
sync100k <= '0';
wait for 450 ns;
sync100k <= '1';
wait for 50 ns;
sync100k <= '0';
wait for 450 ns;
sync100k <= '1';
wait for 50 ns;
sync100k <= '0';
wait for 450 ns;
sync100k <= '1';
wait for 50 ns;
sync100k <= '0';
wait for 450 ns;
sync100k <= '1';
wait for 50 ns;
sync100k <= '0';
wait for 450 ns;
wait for 1000 ns;
end process;
END behavior;
我看到了代码，但是我没有看到此FSM的错误步骤在哪里。任何帮助将不胜感激！