Question

我尝试使用2个进程设计FSM，但我有太多的语法错误。我无法理解有什么不对。大多数错误都是这样的“if / else附近的语法错误”等。

entity myFSM is
    Port ( CLK : in  STD_LOGIC;
           RST : in  STD_LOGIC;
           IN0 : in  STD_LOGIC;
           IN1 : in  STD_LOGIC;
           IN2 : in  STD_LOGIC;
           LED : out  STD_LOGIC_VECTOR (7 downto 0));
end myFSM;

architecture Behavioral of myFSM is
        type state is (A, B, C);
        signal currentS, nextS: state;
myFSM_comb: process (currentS, IN0, IN1, IN2)
begin
    case currentS is
        when A =>   LED <= "11111111";
                        if IN0 = '1' then nextS<=B;
                        else if IN1 = '1' then nextS<=C;
                        else            nextS<=A;
                        end if;
        when B =>   LED <= "11000011";
                        if IN0 = '1' then nextS<=C;
                        else if IN1 = '1' then nextS<=A;
                        else nextS<=B;
                        end if;
        when C =>   LED <= "00111100";
                        if IN0 = '1' then nextS<=A;
                        else if IN1 = '1' then nextS<=B;
                        else nextS<=C;
                        end if;
    end case;
end process;

myFSM_synch: process(CLK,RST)
begin 
    if (RST='1')        then    currentS<=A;
    elsif (rising_edge(CLK)) then; currentS<= nextS;
    end if;
end process ;

end Behavioral;

Answer 1

我可以看到以下错误：

的关键字如果是elsif。
在第一个流程之前缺少begin。
FSM没有初始状态
```
signal currentS : state := A;
```

这是您的代码的固定和改进版本。它使用nextS的默认分配。

myFSM_comb: process (currentS, IN0, IN1, IN2) -- IN2 is unused
begin
   nextS <= currentS;
   LED   <= "11111111";

  case currentS is
    when A =>
      LED <= "11111111";
      if IN0 = '1' then
        nextS<=B;
      elsif IN1 = '1' then
        nextS<=C;
      end if;
    when B =>
      LED <= "11000011";
      if IN0 = '1' then
        nextS<=C;
      elsif IN1 = '1' then
        nextS<=A;
      end if;
    when C =>
      LED <= "00111100";
      if IN0 = '1' then
        nextS<=A;
      elsif IN1 = '1' then
        nextS<=B;
      end if;
  end case;
end process;

使用2个进程在VHDL中设计FSM

1 个答案: