Question

我是新来的，这是我的问题：我有一个状态机有3个状态（s0，s1.s2）和输入:(重置，clk，开始）和输出（完成）。我的状态机工作方式如下：重置时它来到s0，然后如果start = ＆＃39; 1＆＃39;进入s2并且在这种状态下我希望它在这里停留12个时钟周期（12个时钟周期延迟），然后进入s2并完成=＆＃39; 1＆＃39;在这里然后回到s0。我的代码是这样的：

我的代码似乎很好，但我的模拟结果不合适???

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;

ENTITY fsm_count IS
port(clk : in std_logic;
    reset : in std_logic;
    start : in std_logic ;
    don : out std_logic );

END ENTITY fsm_count;

- 建筑弧fsm_count是 type statetype是（s0，s1，s2）; signal pr_state，nx_state：statetype; signal s_counter：std_logic_vector（3 downto 0）：=（其他=＆gt;＆＃39; 0＆＃39;）; - 零

begin
fsmcount: process(clk,reset,pr_state,start)
begin
  if reset = '1'then pr_state <= s0;
  elsif (clk'event and clk='1') then

  case pr_state is 

    when s0 => 
    if start ='1' then nx_state <=s1;
    else nx_state <= s0;
    end if;

   when s1 =>
     s_counter <= s_counter + '1';
     if (s_counter = "1100") then 
       nx_state <= s2;
       s_counter <=(others =>'0'); -- initializing the counter back to zero
     else nx_state <=s1;

     end if;

   when s2 => 
     nx_state<= s0;


  end case;
end if;
 end process fsmcount;

  don <= '1' when  (pr_state = s2) else '0';             
END ARCHITECTURE arc;

Answer 1

我还没有将它合成，但我认为它应该有效。我没有使用VHDL2008，修改条件以便返回bool类型：

ARCHITECTURE arc OF fsm_count IS

  type statetype is (s0,s1,s2);
  signal pr_state,nx_state: statetype;
  signal s_counter: std_logic_vector (3 downto 0);

begin

  process(clk) begin if rising_edge(clk) then
    if rst then pr_state <= s0; else pr_state <= nx_state; end if;
  end if; end process;

  process(clk) begin if rising_edge(clk) then
    if pr_state/=s1 then s_counter <= (others=>'0');
    else s_counter <= s_counter+1; end if;
  end if; end process;

  process(all) begin
    case pr_state is 

     when s0 => 
       if start then nx_state <= s1;
       else nx_state <= pr_state; end if;

     when s1 =>
       if s_counter?=12 then nx_state <= s2;
       else nx_state <= pr_state; end if;

     when s2 => 
       nx_state<= s0;

    end case;
  end process;

  don <= '1' when  (pr_state = s2) else '0';             

END arc;

修改

或者，您可以保存s2（我将pr_state替换为sta，将nx_state替换为stn，将s_counter替换为cnt }}：

ARCHITECTURE arc OF fsm_count IS signal idon: std_logic; type t_st is (s0,s1); signal sta, stn: t_st; signal cnt: std_logic_vector (3 downto 0); begin process(clk) begin if rising_edge(clk) then if rst then sta <= s0; else sta <= stn; end if; end if; end process; process(clk) begin if rising_edge(clk) then if sta/=s1 then cnt <= (others=>'0'); else cnt <= cnt+1; end if; end if; end process; process(all) begin case sta is when s0 => if start then stn <= s1; else stn<=sta; end if; when s1 => if idon then stn <= s0; else stn<=sta; end if; end case; end process; idon <= cnt?=12; don <= idon; END arc;

或者，你可以使用一个标志：

ARCHITECTURE arc OF fsm_count IS signal st, idon: std_logic; signal cnt: std_logic_vector (3 downto 0); begin process(clk) begin if rising_edge(clk) then if sta/=s1 then cnt <= (others=>'0'); else cnt <= cnt+1; end if; end if; end process; idon <= cnt?=12; process(clk) begin if rising_edge(clk) then if rst then st <= '0'; elsif not st and start then st <= '1'; elsif st and idon then st <= '0'; end if; end if; end process; don <= idon; END arc;

带有计数器的VHDL FSM

1 个答案: