值部分传播到中间信号

Question

我有一个名为 inbound 的实体，其中包括另一个名为 entity_A 的实体和一个测试平台 < 入站 的strong> tb 。

我在 tb 中有一个别名，作为 entity_A 的输出，因此我可以按以下方式访问它下方：

ALIAS alias_entity_A_out IS
  <<SIGNAL .tb.inbound_inst.entity_A_inst.entity_A_out : INBOUND_RECORD_TYPE>>; 

我的问题是用于实例化 inbound 中的 entity_A 的输出中间信号（ entity_A_out_inst ） strong> 正在获取 entity_A_out 输出端口的值的一部分，仅分配了两位，其余未初始化，如下所示：

-- Instantiate entity_A
      entity_A_inst : ENTITY work.entity_A(rtl)
        PORT MAP(
          clk          => clk,
          reset        => reset,
          entity_A_in  => entity_A_in_inst,
          entity_A_out => entity_A_out_inst); -- here only part of the values are propogated
    

 # ** Note: rx_data in entity_A_out output port = 00000000
 # ** Note: rx_data in entity_A_out_inst intermediate signal = 00UUUUUU
 # ** Note: alias_rx_data = 00000000

 # ** Note: rx_data in entity_A_out output port = 00000001
 # ** Note: rx_data in entity_A_out_inst intermediate signal = 00UUUUUU
 # ** Note: alias_rx_data = 00000001

这是我的 入站 代码：

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;

PACKAGE inbound_pkg IS

  TYPE RX_PORT_RECORD IS RECORD
    rx_data : UNSIGNED(7 DOWNTO 0);
    valid   : STD_LOGIC;
  END RECORD RX_PORT_RECORD;
  
  TYPE INBOUND_RECORD_TYPE IS RECORD
    rx_port : RX_PORT_RECORD;
  END RECORD INBOUND_RECORD_TYPE;
  
END PACKAGE inbound_pkg;

-----------------------------------------------------------
-----------------------------------------------------------

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE work.inbound_pkg.ALL;

ENTITY entity_A IS
  PORT(clk          : IN  STD_LOGIC;  -- Main clock 
       reset        : IN  STD_LOGIC;  -- reset, active
       entity_A_in  : IN  INBOUND_RECORD_TYPE;
       entity_A_out : OUT INBOUND_RECORD_TYPE);
END ENTITY entity_A;

ARCHITECTURE rtl OF entity_A IS
BEGIN
seq_proc: PROCESS (clk, reset)
  BEGIN -- for seq_proc
    IF (reset = '1') THEN
      entity_A_out.rx_port.rx_data <= (OTHERS => '0');
      entity_A_out.rx_port.valid   <= '0';
    ELSIF rising_edge(clk) THEN
      entity_A_out <= entity_A_in;
    END IF;
  END PROCESS seq_proc;
END ARCHITECTURE;

-----------------------------------------------------------
-----------------------------------------------------------

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE work.inbound_pkg.ALL;

ENTITY inbound IS
  PORT(clk         : IN  STD_LOGIC;  -- Main clock 
       reset       : IN  STD_LOGIC;  -- reset, active
       inbound_in  : IN  INBOUND_RECORD_TYPE;
       inbound_out : OUT INBOUND_RECORD_TYPE);
END ENTITY inbound;

ARCHITECTURE rtl OF inbound IS

  -- INTERNAL SIGNALS DECLARATION --
  SIGNAL entity_A_in_inst  : INBOUND_RECORD_TYPE; 
  SIGNAL entity_A_out_inst : INBOUND_RECORD_TYPE; -- this is the signal that is not working

BEGIN  -- start of architecture --
  -- for entity_A_in
  entity_A_in_inst.rx_port <= inbound_in.rx_port;
  -- for entity_A_out 
  inbound_out.rx_port <= entity_A_out_inst.rx_port;

  -- Instantiate entity_A
  entity_A_inst : ENTITY work.entity_A(rtl)
    PORT MAP(
      clk          => clk,
      reset        => reset,
      entity_A_in  => entity_A_in_inst,
      entity_A_out => entity_A_out_inst
    );
END ARCHITECTURE;

这是我的 tb 代码：

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE work.inbound_pkg.ALL;

ENTITY tb IS
END ENTITY tb;

ARCHITECTURE sim OF tb IS
  SIGNAL clk   : STD_LOGIC := '0';
  SIGNAL reset : STD_LOGIC := '1';
  SIGNAL inbound_in_inst  : INBOUND_RECORD_TYPE := (rx_port => ((others => '0'), '0')); 
  SIGNAL inbound_out_inst : INBOUND_RECORD_TYPE;

ALIAS alias_entity_A_out IS
  <<SIGNAL .tb.inbound_inst.entity_A_inst.entity_A_out : INBOUND_RECORD_TYPE>>; 
  
BEGIN  -- start of architecture --
  
  inbound_inst : ENTITY work.inbound(rtl)
  PORT MAP(
    clk         => clk,
    reset       => reset,
    inbound_in  => inbound_in_inst,
    inbound_out => inbound_out_inst); 
      
  clk   <= NOT clk after 10 ns;
  reset <= '0' after 30 ns;
  
  test : PROCESS 
  begin
    WAIT UNTIL reset = '0'; 
    inbound_in_inst.rx_port.valid   <= '0';
    inbound_in_inst.rx_port.rx_data <= x"01";
    WAIT UNTIL rising_edge(clk);
    
    report "rx_data in entity_A_out output port = " & to_string(alias_entity_A_out.rx_port.rx_data);
    report "rx_data in entity_A_out_inst intermediat signal = " & to_string(<<SIGNAL .tb.inbound_inst.entity_A_out_inst : INBOUND_RECORD_TYPE>>.rx_port.rx_data);
    report "alias_rx_data = " & to_string(alias_entity_A_out.rx_port.rx_data);

    inbound_in_inst.rx_port.rx_data <= x"02";
    WAIT UNTIL rising_edge(clk);
    
    report "rx_data in entity_A_out output port = " & to_string(alias_entity_A_out.rx_port.rx_data);
    report "rx_data in entity_A_out_inst intermediat signal = " & to_string(<<SIGNAL .tb.inbound_inst.entity_A_out_inst : INBOUND_RECORD_TYPE>>.rx_port.rx_data);
    report "alias_rx_data = " & to_string(alias_entity_A_out.rx_port.rx_data);
    
    WAIT UNTIL rising_edge(clk);
    
    wait for 100 ns;
  END PROCESS test;
END ARCHITECTURE sim;

我不明白这里出了什么问题，但是当我不使用 Alias 并在 tb < / strong> 并使用外部名称进行分配，效果如下：

SIGNAL entity_A_out: INBOUND_RECORD_TYPE;
entity_A_out <= <<SIGNAL .tb.inbound_inst.entity_A_inst.entity_A_out : INBOUND_RECORD_TYPE>>; 

在这里您可以在EDA中看到它

https://www.edaplayground.com/x/2CMT

Answer 1

您的代码看起来有效，因此这一定是模拟器的错误。如果您在EDA Playground中切换到Riviera-PRO，它将按预期工作。