Question

我正在研究一个Sequencer，我无法弄清楚如何增加一些输出信号。在状态1（S1）中，我想增加ram_add_wr（在每个时钟周期）。

clocked_process:PROCESS(clk,rst)
    VARIABLE count: INTEGER RANGE 0 TO 32;
BEGIN  
      IF (rst = '0') THEN  
          pr_state <= idle; 
          count := 0;
      ELSIF (clk'event AND clk='1') THEN    
          count := count+1;
          IF (count>=timer) THEN
              pr_state <= nx_state;
              count := 0;
          END IF;
      END IF;
END PROCESS;        

PROCESS(pr_state, en) 
BEGIN         
    CASE pr_state IS
        WHEN idle =>  
        timer <= 1;
            IF (en = '1') THEN
                sig_ram_add_wr <= "00000";  
                nx_state <= s1;  
            ELSE
                nx_state <= idle;
                sig_ram_add_wr <= "00000";  
    END IF;

        WHEN s1 =>           
        timer <= 32;
            IF (en ='1') THEN
        --timer <= 1;

Answer 1

您可以使用两个计数器寄存器。

   ...
   signal cntReg, cntReg_next: integer range 0 to 31 := 0;

begin

   -- Clocked process --
   ...
   elsif (clk'event and clk='1') then
       if (pr_state = s1) then
           cntReg <= cntReg_next;
       end if;
       ...
   ...


   -- Combined process --
   ...
   when s1 =>
      cntReg_next <= cntReg + 1;
   ...

   -- output (depends on the type of sig_ram_add_wr)
   sig_ram_add_wr <= std_logic_vector(to_unsigned(cntReg, 5));

在其他州，您需要将cntReg和cntReg_next都重置为0.

Answer 2

无需单独的流程 - 执行以下操作：

clocked_process:PROCESS(clk,rst)

    VARIABLE count: INTEGER RANGE 0 TO 32;
    variable addr : unsigned(sig_ram_add_wr'range);
BEGIN  

      IF rst = '0' THEN  
          ...
          addr := (others => '0';
      ELSIF rising_edge(clk) THEN    
          ...
          if pr_state = s1 then
             addr := addr + 1; -- update the address counter here
          end if;
          ...
      END IF;
      sig_ram_add_wr <= std_logic_vector(addr); -- copy it onto the output pins here - as this is outside the clocked element, the synthesiser will just create a wire
END PROCESS;

其他说明：

if条件
如果rst处于低电平状态，我会在信号/引脚名称中指出（我通常使用_n后缀，所以rst_n

VHDL序列：在FSM中递增输出信号

2 个答案: