VHDL电源定序器

Question

我正在尝试用VHDL创建一个电源序列器，这是我的代码：

library IEEE;

use IEEE.std_logic_1164.all;

entity PowerSeq is
    port (
            RESET : out std_logic;
            POWER : out std_logic;
            EN : out std_logic;
            CLOCK : out std_logic;
            SERIAL : out std_logic;
            ModuleEN : in std_logic;
            ModuleCLK : in std_logic
    );
end PowerSeq;

architecture ArchiPowerSeq of PowerSeq is
    signal counter :integer :=0;
    signal StopCount :std_logic := '0';

    begin
        process(ModuleCLK)
        begin
            if ModuleEN = '0' then
                    RESET <= '0';
                    POWER <= '1';
                    EN <= '0';
                    CLOCK <= '0';
                    SERIAL <= '0';
            end if;
            if (rising_edge(ModuleCLK) and StopCount = '0') then
                counter <= counter + 1;
            end if;
            -- 1ms = 250000
            case counter is
                when 2500000 =>
                    EN <= '1';
                when 5000000 =>
                    POWER <= '0';
                when 7500000 =>
                    CLOCK <= '1';
                when 10000000 =>
                    RESET <= '1';
                when 12500000=>
                    SERIAL <= '1';
                    StopCount <= '1';
                when others =>
            end case;

end process;

end ArchiPowerSeq;

我有一个250Mhz的输入时钟（例如，我也尝试降低50Mhz。）

模拟PowerSeq VHDL代码的工作方式与预期的一样，但是当我合成它并在仿真工具中模拟合成代码时，我有正确的EN输入和时钟输入但我输出的所有X都是。编程设备我的输出被这个值阻止：

RESET <= '0';
POWER <= '1';
EN <= '0';
CLOCK <= '0';
SERIAL <= '0';

此代码有什么问题？

第一条评论建议的更新代码：

library IEEE;

use IEEE.std_logic_1164.all;

entity PowerSeq is
    port (
            RESET : out std_logic;
            POWER : out std_logic;
            EN : out std_logic;
            CLOCK : out std_logic;
            SERIAL : out std_logic;
            ModuleEN : in std_logic;
            ModuleCLK : in std_logic
    );
end PowerSeq;

architecture ArchiPowerSeq of PowerSeq is
    signal counter :integer :=0;
    signal StopCount :std_logic := '0';

    begin
        process(ModuleCLK)
        begin
            if (rising_edge(ModuleCLK) and StopCount = '0') then
               if ModuleEN = '0' then
                   RESET <= '0';
                   POWER <= '1';
                   EN <= '0';
                   CLOCK <= '0';
                   SERIAL <= '0';
               end if;
               counter <= counter + 1;

            -- 1ms = 250000
               case counter is
                when 2500000 =>
                    EN <= '1';
                when 5000000 =>
                    POWER <= '0';
                when 7500000 =>
                    CLOCK <= '1';
                when 10000000 =>
                    RESET <= '1';
                when 12500000=>
                    SERIAL <= '1';
                    StopCount <= '1';
                when others =>

               end case;
             end if;
       end process;

end ArchiPowerSeq;