Question

我正在使用VHDL实现一个简单的FSM。我用VHDL出来了这个代码，我得到了这个错误：'非解析信号NS有多个来源'。我深深研究了代码但是没有弄清楚错误任何人都可以帮我解决这个问题吗？

                     library ieee ;
                     use ieee.std_logic_1164.all ;
                     entity MeallyMachine is
                     port( 
                     x,res,clk:in std_logic;
                     z1,z2:out std_logic       
                     );

                    end MooreMachine;


                    architecture M1 of MooreMachine is
                    type state_type is(s0,s1,s2,s3);
                    signal PS,NS:state_type;

                     begin
                     ETAT:process(PS,x)
                     begin
                     case PS is
                      when  s0=>  if (x='0') then
                      NS<=s0;
                                 elsif (x='1') then
                                 NS<=s1;
                                 end if;
                     when s1=>  if (x='0') then
                      NS<=s1;
                                elsif (x='1') then
                      NS<=s2;
                                end if;  
                     when s2=>  if (x='0') then
                     NS<=s2;
                                elsif (x='1') then
                     NS<=s3;
                                 end if;
                     when s3=>  if (x='0') then
                     NS<=s3;
                                 elsif (x='1') then
                     NS<=s0;
                                 end if;
                     end case;
                   end process ETAT;
                Sortie:process(PS,x)
                  begin
                   case PS is
                      when s0=>  
                            z1<='1';
                        if (x='0') then
                            z2<='0';
                         elsif (x='1') then
                            z2<='1';
                          end if;
                      when s1=>   
                            z1<='1';
                       if (x='0') then
                            z2<='0';
                       elsif (x='1') then
                        z2<='1';
                       end if;  
                     when s2=>  z1<='0';
                      if (x='0') then
                        z2<='0';
                      elsif (x='1') then
                        z2<='1';
                      end if;
                   when s3=>   z1<='1';
                        if (x='0') then
                         z2<='0';
                        elsif (x='1') then
                         z2<='1';
                        end if;
                   end case;
                end process Sortie;
           Horloge:process(clk,res,NS)
                begin
                 if (res='0') then
                      NS<=s0;
                 elsif (rising_edge(clk)) then 
                      PS<=NS;
                 end if;
                 end process Horloge;




         end M1;

Answer 1

您的错误消息：non resolved signal NS has multiple sources还包含源代码行，这会导致多个驱动程序问题。请参阅完整的Xilinx XST综合报告。

此外，您的代码有多个复制粘贴错误：

entity MeallyMachine is应为entity MooreMachine is，因为您的架构引用了MoorMachine
NS<=s0;应为PS<=s0;以解决多个驱动程序问题
您的FSM不是Moore FSM，因为输出取决于当前状态和输入process(PS,x)

非解析信号具有多个源VHDL

1 个答案: