Question

我正在尝试编写一个程序来检测给定输入是否为素数。当我运行测试台时，我得到了正确的结果，但是当我在FPGA上运行它时，它只能识别可被整除的数字3或甚至不是素数。任何数字，如25可以被5整除，将导致isPrime为1.什么可能导致这种不一致的结果？

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE IEEE.std_logic_unsigned.all;
USE IEEE.numeric_std.all;


entity PrimeNumber is
  Port ( clk: in std_logic;
         rst : in std_logic;
         input: in std_logic_vector(15 downto 0);
         isPrime: out std_logic:= '0';
         testOut: out std_logic_vector(31 downto 0)

     );
end PrimeNumber;

architecture Behavioral of PrimeNumber is
SIGNAL current_state: std_logic_vector(2 downto 0);
signal next_state: std_logic_vector(2 downto 0):= "000";
signal max: integer;
signal temp: integer;
signal x: integer;
signal nextX:integer;
signal localPrime : std_logic:= '0';
signal current : integer;
signal update: std_logic := '0';
begin

nextX <= x +2;
process(current_state,input)
begin
case (current_state) is

when "000" => --Initial State
        update <= '0';
        localPrime <= '0';
        if(input < x"0004")then
            next_state <= "111";

        else
            max <= to_integer(unsigned(input(15 downto 1)));
            current <=to_integer(unsigned(input));
            if(input(0) = '0')then
                next_state <= "110";
             else
                next_state <= "001";
             end if;
        end if;
when "001" =>  -- Computation State

        localPrime <= '0';
        temp <=  current mod x;
        if(x > max) then
            next_state <= "111";
        else
            next_state <= "010";
        end if;
        update <= '1';


when "010" => -- Checking State
        update <= '0';
        localPrime <= '0';
        if(temp = 0) then
            next_state <= "110";
        else
            next_state <= "001";
        end if;


when "110" => 
           localPrime <= '0'; -- Not Prime State
           next_state <= "110";

when "111" => 
            update <= '0';
           localPrime <= '1'; --Prime State
            next_state <= "111";

when others => 
        temp <= 0;
        localPrime <= '0';
        next_state <= "000";
end case;

end process;


Update_Registers: process(clk)
begin

if(clk'event and clk = '1') then
    if ( rst = '1') then
    current_state <= "000";    
    isPrime <= '0';
    x<=3;
else
    if(update = '1') then
        x <= nextX;
    end if;
    current_state <= next_state;
    isPrime <= localPrime;
end if;
end if;

end process;


end Behavioral;

Answer 1

快速检查sim / syn不匹配，以及在HW之外需要的可见性：将mod结果输出到一个端口，sim，仍然应该“工作”...同步，编译你的（希望，verilog）网表为TB ，指向编译的网表，sim，检查RTL /预期结果的mod结果。

VHDL测试平台工作但在FPGA上运行时结果不正确

1 个答案: