Question

我在尝试测试我的VHDL时遇到了一些问题。我使用fpga Baysis 2来运行我的代码，它在硬件上工作得很好，但是当我使用程序Isim来模拟我的代码时，它并没有显示我的输出引脚的任何行为，只有字母U。

我正在通过互联网查找并无法找到解决方案，有人可以帮我解决这个问题吗？

以下是我的代码的最后一部分（可能是错误的一部分）。在此之前，代码只是有一个过程将时钟分频为1秒，以1/200秒的速度进行分频，以快速打开和关闭fpga显示屏上的LED，并对其进行计数。当然，让24小时工作的时间是秒。

.py

以下是测试台 LIBRARY ieee; 使用ieee.std_logic_1164.ALL;

    contador: process(clk200)

variable flag : std_logic_vector (1 downto 0);
-- ledplex is the mux that controls which display should be on
-- Segm is the 7 segments display 
-- mu md hu hd are the signals with the time information
begin

if(clk200'event and clk200='1') then
     if (flag = "00") then

        ledplex <= "1110";

            case mu is 
                when 0 => segm <= "1000000";
                when 1 => segm <= "1111001";
                when 2 => segm <= "0100100";
                when 3 => segm <= "0110000";
                when 4 => segm <= "0011001";
                when 5 => segm <= "0010010";
                when 6 => segm <= "0000011";
                when 7 => segm <= "1111000";
                when 8 => segm <= "0000000";
                when 9 => segm <= "0011000";
                when others => segm <= "1111111";   
            end case;
        flag := "01";

    elsif (flag = "01") then

        ledplex <= "1101";

            case md is 
                when 0 => segm <= "1000000";
                when 1 => segm <= "1111001";
                when 2 => segm <= "0100100";
                when 3 => segm <= "0110000";
                when 4 => segm <= "0011001";
                when 5 => segm <= "0010010";
                when others => segm <= "1111111";           
            end case;
    flag := "10";

    elsif (flag = "10") then
        ledplex <= "1011";

            case hu is 
                when 0 => segm <= "1000000";
                when 1 => segm <= "1111001";
                when 2 => segm <= "0100100";
                when 3 => segm <= "0110000";
                when 4 => segm <= "0011001";
                when 5 => segm <= "0010010";
                when 6 => segm <= "0000011";
                when 7 => segm <= "1111000";
                when 8 => segm <= "0000000";
                when 9 => segm <= "0011000";
                when others => segm <= "1111111";   
            end case;
        flag := "11";

    elsif (flag = "11") then
        ledplex <= "0111";

            case hd is 
                when 0 => segm <= "1000000";
                when 1 => segm <= "1111001";
                when 2 => segm <= "0100100";
                when others => segm <= "1111111";           
            end case;
    flag := "00";

    end if;
end if;
end process contador;

Answer 1

您没有初始化变量flag。如果没有这个，你的变量可能是未定义的，因此U。使用以下内容：

variable flag : std_logic_vector (1 downto 0) := "00"; -- initialize variable

我怎样才能测试VHDL 24小时时钟？

1 个答案: