VHDL加法器测试台

时间:2013-09-06 18:23:05

标签: vhdl

我是VHDL的新手,我正在使用4个全加器制作一个4位加法器。我创建了一个测试平台,看看加法器是否正常工作,并且我正在获得UUUU的值。从我读到的是该过程没有被执行。我不知道如何解决这个问题,任何帮助将不胜感激。

这是TestBench

ENTITY Adder4_Test IS
END Adder4_Test;

ARCHITECTURE behavior OF Adder4_Test IS 

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT Adder4
PORT(
     X : IN  STD_LOGIC_vector(3 downto 0);
     Y : IN  STD_LOGIC_vector(3 downto 0);
     Ans : OUT STD_LOGIC_VECTOR(3 downto 0);
     Cout : OUT STD_LOGIC
    );
END COMPONENT;


--Inputs
signal X : STD_LOGIC_vector(3 downto 0) := (others => '0');
signal Y : STD_LOGIC_vector(3 downto 0) := (others => '0');


--Outputs
signal Ans : STD_LOGIC_vector(3 downto 0);
signal Cout : STD_LOGIC;
-- No clocks detected in port list. Replace <clock> below with 
-- appropriate port name 

--constant <clock>_period : time := 10 ns;

BEGIN

-- Instantiate the Unit Under Test (UUT)
uut: Adder4 PORT MAP (
      X,
      Y, 
      Ans,
      Cout
    );

-- Clock process definitions
--<clock>_process :process
--begin
    --<clock> <= '0';
    --wait for <clock>_period/2;
    --<clock> <= '1';
    --wait for <clock>_period/2;
--end process;


-- Stimulus process
stim_proc: process
begin       
  -- hold reset state for 100 ns.
  --wait for 100 ns;    

  --wait for <clock>_period*10;

  -- insert stimulus here 

    -- Case 1 that we are testing.
        X <= "0000";
        Y <= "0000";
        wait for 10 ns;
        assert ( Ans = "0000" )report "Failed Case 1 - Ans" severity error;
        assert ( Cout = '0' )   report "Failed Case 1 - Cout" severity error;
        wait for 40 ns;

    -- Case 2 that we are testing.

        X <= "1111";
        Y <= "1111";
        wait for 10 ns;
        assert ( Ans = "1110" )report "Failed Case 2 - Ans" severity error;
        assert ( Cout = '1' )   report "Failed Case 2 - Cout" severity error;
        wait for 40 ns;



  wait;
 end process;

 END;

这是Adder4

entity Adder4 is
Port ( X : in  STD_LOGIC_vector (3 DOWNTO 0);
       Y : in  STD_LOGIC_vector (3 DOWNTO 0);
       Ans: out  STD_LOGIC_vector (3 DOWNTO 0);
          Cout: out STD_LOGIC);
end Adder4;

architecture Structure of Adder4 is

component FullAdder is
Port ( X : in STD_LOGIC;
       Y : in STD_LOGIC;
       Cin : in STD_LOGIC;
          Sum : out STD_LOGIC;
          Cout : out STD_LOGIC);
end  component;

signal c0, c1, c2, c3: STD_LOGIC;

  begin
c0 <='0';
b_adder0: FullAdder port map (X(0), Y(0), c0, Ans(0), c1);
b_adder1: FullAdder port map (X(1), Y(1), c1, Ans(1), c2);
b_adder2: FullAdder port map (X(2), Y(2), c2, Ans(2), c3);
b_adder3: FullAdder port map (X(3), Y(3), c3, Ans(3), Cout);


 end Structure;

这是FullAdder

entity FullAdder is
Port ( X : in  STD_LOGIC;
       Y : in  STD_LOGIC;
       Cin : in  STD_LOGIC;
       Sum : out  STD_LOGIC;
       Cout : out  STD_LOGIC);
end FullAdder;

 architecture Behavioral of FullAdder is

component Xor_Model is
Port ( A : in  STD_LOGIC;
       B : in  STD_LOGIC;
       C : in  STD_LOGIC;
       Z : out  STD_LOGIC);
end  component;



  begin

Cout <= ((X and Y) or (Y and Cin) or (X and Cin));
Sum <= (X AND (NOT Y) AND (NOT Cin)) OR ((NOT X) AND Y AND (NOT Cin)) OR
((NOT X) AND (NOT Y) AND Cin) OR (X AND Y AND Cin) after 5ns;
xorLabel: Xor_Model
    Port Map ( A => X, B => Y, C => Cin, Z => Sum);


 end Behavioral;

1 个答案:

答案 0 :(得分:2)

在添加了你没有提供的上下文子句之后,将5ns分成5 ns并确保Addr4中所需的实体按正确的顺序进行分析,我尝试使用ghdl运行模拟,我立即收到错误消息“

Adder4.vhdl:28:1:warning: component instance "xorlabel" is not bound
Adder4.vhdl:12:15:warning: (in default configuration of fulladder(behavioral))

这适用于FullAdder。看到它是一个3输入异或,我添加了一个:

library ieee;
use ieee.std_logic_1164.all;

entity Xor_model is
    Port (A:    in  std_logic;
          B:    in  std_logic;
          C:    in  std_logic;
          Z:    out std_logic
    );
end entity;

architecture behavioral of Xor_model is
begin
    Z <= A xor B xor C;
end behavioral;

从FullAdder中的Sum赋值延迟开始,直到5 ns才会出现'U'。

我在相同的延迟分配后5 ns后清除了50秒的'X'。请注意,由于短路逻辑运算符,LSB为“0”。

将FF添加到FF得到了FE(正确而不考虑正确显示为'1'的进位)。

摆脱最初的'U'可以通过以下两种方式之一完成。将Sum的已知值指定为默认值,而不是依赖于默认值,或将赋值中的延迟移除为Sum。

'X'依赖于FullAdders的Sum,等待5 ns时输入转换。

Addr4_Test waveform

在行为组合模型中,延迟不是特别富有表现力,特别是当您不使用子项延迟时。如果您根据门延迟延迟提供信号,然后延迟特定网络的信号路径,则Sum将显示正确的累积延迟时间。您还可以使用无延迟生成的中间Sum(具有不同的信号名称),并在延迟后将其分配给输出端口Sum,从而消除'X'。从FullAdder移动5 ns后到Adder4:

在FullAdder中:

((NOT X) AND (NOT Y) AND Cin) OR (X AND Y AND Cin) ; --after 5 ns;

在Adder4中:

architecture Structure of Adder4 is
signal sum: std_logic_vector(3 downto 0);

b_adder0: FullAdder port map (X(0), Y(0), c0, sum(0), c1);
b_adder1: FullAdder port map (X(1), Y(1), c1, sum(1), c2);
b_adder2: FullAdder port map (X(2), Y(2), c2, sum(2), c3);
b_adder3: FullAdder port map (X(3), Y(3), c3, sum(3), Cout);

并添加延迟为ans分配总和:

Ans&lt; = 5 ns后的总和;

Moved Delay to Adder4

如果你在Adder4端口的Ans上设置默认值'0',那么

   Ans: out  STD_LOGIC_vector (3 DOWNTO 0) := (others => '0');

你可以摆脱最初的'U':

get rid of UUUU

并且澄清'U'是存在的,直到在5 ns延迟之后输出(Ans)上有事务。使用它可能更合适(其他=&gt;'X')