Question

如何为此完整加法器代码制作测试平台。我是新手，非常感谢你的帮助。

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Full_Adder is

PORT(a , b , C_In : IN STD_LOGIC; S,C_Out : OUT STD_LOGIC);

end Full_Adder;

architecture Behavioral of Full_Adder is
begin

S <= a XOR b XOR C_In;
C_Out <= (a AND b) OR (a AND C_In) OR (b AND C_In);

end Behavioral;

Answer 1

这是一个很好的reference，是我搜索如何编写测试平台时出现的第一个。{ 你应该首先谷歌，给它一个诚实的镜头，然后回到这里更具体的问题。

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Full_Adder_tb is     
end Full_Adder_tb;

architecture Behavioral of Full_Adder_tb is

   component Full_Adder is -- component declaration
   port(
      a : in std_logic;
      b : in std_logic;
      C_in : in std_logic;
      S : out std_logic;
      C_out : out std_logic
   );
   end component;

   signal a: std_logic := '0'; -- signal declarations
   signal b: std_logic := '0';
   signal C_in: std_logic := '0';
   signal S: std_logic;
   signal C_out : std_logic;

begin

   uut : Full_Adder -- component instantiation
   port map(
      a => a, -- signal mappings
      b => b,
      C_in => C_in,
      S => S,
      C_out => C_out);

process 
begin 
   wait 10 ns; -- wait time 
   a <= '0'; b <= '0'; C_in <= '1'; -- example test vector
   wait 10 ns;

   -- Other test vectors and waits here

end process;


end Behavioral;

如何为全加器创建测试平台代码？

1 个答案: