Question

我有一个以VHDL实现的基本摩尔斯电码解码器设计。它在FPGA板上可以正常工作，但不能在测试台上工作。

我猜按钮有问题，但是我不确定。

我尝试在测试台上使用时钟时间无济于事。

ARCHITECTURE behavior OF ProjTest IS 

    -- Component Declaration for the Unit Under Test (UUT)

    COMPONENT LabProject
    PORT(
         char : IN  std_logic_vector(4 downto 0);
         save : IN  std_logic;
         start_read : IN  std_logic;
         clk : IN  std_logic;
         p_out : OUT  std_logic
        );
    END COMPONENT;


   --Inputs
   signal char : std_logic_vector(4 downto 0) := (others => '0');
   signal save : std_logic := '0';
   signal start_read : std_logic := '0';
   signal clk : std_logic := '0';

    --Outputs
   signal p_out : std_logic := '0';

   -- Clock period definitions
   constant clk_period : time := 2 ns;

    constant wait_time : time :=  10 ns;

BEGIN

    -- Instantiate the Unit Under Test (UUT)
   uut: LabProject PORT MAP (
          char => char,
          save => save,
          start_read => start_read,
          clk => clk,
          p_out => p_out
        );

   -- Clock process definitions
   clk_process :process
   begin
        clk <= '0';
        wait for clk_period/2;
        clk <= '1';
        wait for clk_period/2;
   end process;


   -- Stimulus process
   stim_proc: process
   begin        

        wait for wait_time;
        char <= "00001";
        wait for wait_time;
        save <= '1';
        wait for wait_time;
        save <= '0';

        wait for wait_time;
        char <= "00010";
        wait for wait_time;
        save <= '1';
        wait for wait_time;
        save <= '0';
      wait for wait_time;

        char <= "00000";
        wait for wait_time;
        save <= '1';
        wait for wait_time;
        save <= '0';
        wait for wait_time;

        start_read <= '1';
        -- wait for wait_time;
        -- start_read <= '0';

      wait;
   end process;

END;

这是整个测试台。 start_read和save信号由FPGA上的按钮控制。

p_out信号应该一点一点地给出给定字母的摩尔斯电码表示，但在测试台上它永远不会改变。如前所述，FPGA上没有问题。

如何在VHDL测试台中模拟按钮？

0 个答案: