VHDL for test在测试台上运行真值表

Question

如何在VHDL测试平台中执行此操作以运行多路复用器的真值表。我是在正确的轨道上吗？

sel <= "00" after 100 ns, "01" after 200 ns, "10" after 300 ns, "11" after 400;

process (sel)
    variable p :STD_LOGIC_VECTOR(3 downto 0); 
begin
    p := "0000"
    for j in "0001" to "1111" loop
        if j /= "1111" then p:= p + 1;
        wait for 5 ns; 
    end loop ;
end process;

x <= p;

Answer 1

将sel（选择）和p（数据）生成在一起，因为它更容易 如果这些不是在不同的情况下解耦，则以正确的时间生成 分配或处理。可以基于自然范围创建循环。该 过程可以是：

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
...
process is
begin
  for sel_loop in 0 to 2 ** sel'length - 1 loop  -- 0 to 3 for sel'length = 2
    for p_loop in 0 to 2 ** p'length - 1 loop  -- 0 to 15 for p'length = 4
      sel <= std_logic_vector(to_unsigned(sel_loop, sel'length));
      p   <= std_logic_vector(to_unsigned(p_loop, p'length));
      wait for 5 ns;
    end loop;
  end loop;
  wait;
end process;

波形如下。