Question

假设我有一个带输出的门。问题是我想连接其输出以及其他几个组件。所以我需要从这个和门做出许多“副本”输出，这样我就可以将许多组件连接到这个输出。你能用信号和别名做这个吗？或者你是怎么做到的？

Answer 1

您可能希望找到介绍性VHDL参考。您可以尝试用Google搜索 VHDL Made Easy ，这是David Pellerin和Douglas Taylor的一本书。

不，你不需要复制。每个'网'只需要一个唯一的信号。

来自des.vhdl：

DB1: bidir port map (Z => DATA(7),Y => DIN(1), OE => DOE, A => DOUT(1));
DB2: bidir port map (Z => DATA(6),Y => DIN(2), OE => DOE, A => DOUT(2));
DB3: bidir port map (Z => DATA(5),Y => DIN(3), OE => DOE, A => DOUT(3));
DB4: bidir port map (Z => DATA(4),Y => DIN(4), OE => DOE, A => DOUT(4));
DB5: bidir port map (Z => DATA(3),Y => DIN(5), OE => DOE, A => DOUT(5));
DB6: bidir port map (Z => DATA(2),Y => DIN(6), OE => DOE, A => DOUT(6));
DB7: bidir port map (Z => DATA(1),Y => DIN(7), OE => DOE, A => DOUT(7));
DB8: bidir port map (Z => DATA(0),Y => DIN(8), OE => DOE, A => DOUT(8));

DO_EN:  invbuf port map ( A => DOE_N, Z => DOE);

组件声明：

package des_pack is


    component bidir
        port (
            Z:      inout   std_logic;
            Y:      out std_logic;
            OE:     in  std_logic;
            A:      in  std_logic
        );
    end component;
...

    component invbuf
        port (
            A:      in  std_logic;
            Z:      out std_logic
        );

信号DOE声明：

architecture behave of des is
...
    signal DOE:                 std_logic;
...
begin

这是来自DES的VHDL实现，即GPLv3。 https://dl.dropboxusercontent.com/u/25980826/vhdl_des.tar.gz

Answer 2

不，您不需要复制 - 任何其他数量的东西都可以“收听”特定信号。例如：

....
architecture a of entity_name is
  signal and_out : std_logic;
begin
  -- drive the signal we want to use in multiple places, just a normal signal assignment
  and_out <= in1 and in2; 

  -- one block using the signal
  some_block_instance: entity work.some_block
  port map (some_input => and_out,...); 

  -- another block using the signal
  some_other_block_instance: entity work.some_other_block
  port map (some_other_input => and_out,...);

  another_signal <= and_out or in3; -- a signal assignment reading the signal
....

Answer 3

您说您想要将AND门输出连接到许多其他组件。你是迂腐的，你实际上会将它连接到这些组件上的端口：我们可以假设所有这些端口都是输入端口吗？如果是的话......

创建一个简单的信号，只需将其连接到输出端口和所有输入端口。马丁用细节打败了我......

VHDL - 如何将1个输出位连接到多个1位信号？

3 个答案: