VHDL 1位ALU - 行为

Question

我刚用行为方式编写了这个1位ALU的代码。代码包含溢出检查。如果代码正确，有人可以解释一下吗？ 这是代码：

entity ALU_VHDL is
port
(
  a, b: in std_logic_vector(1 downto 0);
  Operation : in std_logic_vector(2 downto 0);

  Carry_Out : out std_logic;
  Flag : out std_logic;
  Result : out std_logic_vector(1 downto 0)
  );
 end entity ALU_VHDL;

 architecture Behavioral of ALU_VHDL is

signal Temp: std_logic_vector(2 downto 0);

begin

process(a, b, Operation, temp) is
begin
  Flag <= '0';
  case Operation is
 when "000" => -- resu = a + b, flag = carry = overflow
    Temp   <= std_logic_vector((unsigned("0" & a) + unsigned(b)));
        Result <= temp(1 downto 0);
    Carry_Out   <= temp(2);
 when "001" => -- resu = |a - b|, flag = 1 iff a > b
    if (a >= b) then
       Result <= std_logic_vector(unsigned(a) - unsigned(b));
       Flag   <= '0';
        else
       Result <= std_logic_vector(unsigned(a) - unsigned(b));
       Flag   <= '1';
        end if;
 when "010" =>
    Result <= a and b;
 when "011" =>
    Result <= a or b;
 when "100" =>
    Result <= a xor b;
 when "101" =>
    Result <= not a;
 when "110" =>
        Result <= not b;
 when others => -- resu = a + not b + 1, flag = 0
    Temp   <= std_logic_vector((unsigned("0" & Nibble1) + unsigned(not Nibble2)) + 1);
    Result <= temp(1 downto 0);
    Flag   <= temp(2);
  end case;
end process;

end architecture Behavioral;

我是VHDL的新手，所以任何建议都表示赞赏。提前谢谢。