我需要创建一个32位ALU,具有alu功能,以及adder / Sub,shifter和比较器。 当alu函数为0001时,它转到加法器, 当alu函数是0010时,它转到sub, 当alu函数为1001时,它转到逻辑移位器左b-alu位, 当alu函数是1010时,它转到逻辑移位器右b-alu位,依此类推。
我已经有32位加法器/子和32位移位器代码。
包c31L_pack是
library ieee;
use ieee.std_logic_1164.all;
package c31L_pack is
constant ZERO : std_logic_vector(31 downto 0) :=
"00000000000000000000000000000000";
constant ONES : std_logic_vector(31 downto 0) :=
"11111111111111111111111111111111";
constant BW : integer:=32;
constant SEL3 : integer:=3;
constant SEL1 : integer:=1;
constant OP : integer:=16;
constant reg_field: integer:=6;
constant immediate_size: integer:=15;
subtype alu_function_type is std_logic_vector(3 downto 0);
constant alu_nop : alu_function_type := "0000";
constant alu_add : alu_function_type := "0001";
constant alu_sub : alu_function_type := "0010";
constant alu_comp : alu_function_type := "0011";
constant alu_slt : alu_function_type := "0100";
constant alu_and : alu_function_type := "0101";
constant alu_or : alu_function_type := "0110";
constant alu_not : alu_function_type := "0111";
constant alu_xor : alu_function_type := "1000";
constant alu_shift_logic_left : alu_function_type := "1001";
constant alu_shift_logic_right : alu_function_type := "1010";
constant alu_shift_arith_left : alu_function_type := "1011";
constant alu_shift_arith_right : alu_function_type := "1100";
constant alu_mov : alu_function_type := "1101";
type mux_in_16 is array((OP-1) downto 0) of std_logic_vector(BW-1 downto 0);
type mux_in_2 is array(1 downto 0) of std_logic_vector(BW-1 downto 0);
end;
1位:
library ieee;
use ieee.std_logic_1164.all;
entity adder1 is
port(a : in std_logic;
b : in std_logic;
cin : in std_logic;
sum_def : out std_logic;
carry_borrow : out std_logic);
end;
architecture logic of adder1 is
begin
process(a,b,cin)
begin
sum_def <=a xor b xor cin;
carry_borrow<=(a and b) or (a and cin) or (b and cin);
end process;
end architecture; --architecture logic
和32位加法器/子
library ieee;
use ieee.std_logic_1164.all;
use work.c31L_pack.all;
entity adder32 is
port(a3_32 : in std_logic_vector(BW-1 downto 0);
b3_32 : in std_logic_vector(BW-1 downto 0);
cin : in std_logic;
sub : in std_logic;
sum_32 : out std_logic_vector(BW-1 downto 0);
cout : inout std_logic;
ov : out std_logic);
end;
architecture logic of adder32 is
component adder1
port(a : in std_logic;
b : in std_logic;
cin : in std_logic;
sum_def : out std_logic;
carry_borrow : out std_logic);
end component;
for add1: adder1 use entity work.adder1(logic);
signal carry_i :std_logic_vector(BW-2 downto 0):=(others=>'0');
signal xor_out :std_logic_vector(BW-1 downto 0):=(others=>'0');
signal oz :std_logic;
begin
Exclusive_or:for i in BW-1 downto 0 generate
begin
xor_out(i)<=b3_32(i) xor sub after 19ns;
end generate;
add1: adder1 port map(a=>a3_32(0),b=>xor_out(0),cin=>sub,sum_def=>sum_32(0),carry_borrow=>carry_i(0));
add_2_31 : for i in 1 to BW-2 generate
add1 :adder1 port map(a=>a3_32(i),b=>xor_out(i),cin=>carry_i(i-1),sum_def=>sum_32(i),carry_borrow=>carry_i(i));
end generate;
add32: adder1 port map(a=>a3_32(BW-1),b=>xor_out(BW-1),cin=>carry_i(BW-2),sum_def=>sum_32(BW-1),carry_borrow=>cout);
oz<=carry_i(BW-2) xor cout after 19 ns;
with oz select
ov <= 'Z' when "1",
'0' when "0";
end architecture; --architecture logic
我试图在使用功能代码找出输出之后得到每个结果,我得到了很多错误,我试图找到解决方法。我该怎么办? 感谢你的帮助。我只想先添加add和sub,以便我知道该怎么做。
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.c31L_pack.all;
ENTITY alu32 IS
GENERIC (BW : INTEGER :=32);
PORT ( a_alu32 : in STD_LOGIC_VECTOR (BW -1 downto 0);
b_alu32 : in STD_LOGIC_VECTOR (BW -1 downto 0);
alu_op : in alu_function_type ;
g : out STD_LOGIC ;
e : out STD_LOGIC ;
l : out STD_LOGIC ;
o_alu32 : out STD_LOGIC_VECTOR (BW -1 downto 0);
c_alu32 : inout STD_LOGIC ;
ov_alu32 : out STD_LOGIC );
end alu32;
architecture Behavioral of alu_32 is
component adder32
port(a3_32 : in std_logic_vector(BW-1 downto 0);-<std_logic_vector> is not declared.
b3_32 : in std_logic_vector(BW-1 downto 0);-<std_logic_vector> is not declared.
cin : in std_logic;-<std_logic> is not declared.
sub : in std_logic;-<std_logic> is not declared.
sum_32 : out std_logic_vector(BW-1 downto 0);
cout : inout std_logic;
ov : out std_logic);
end component;
signal o1:std_logic_vector(BW-1 downto 0);
signal c1:std_logic;
signal ov1:std_logic;
signal o2:std_logic_vector(BW-1 downto 0);
signal c2:std_logic;
signal ov2:std_logic;
begin
adder32 port map(a3_32=>a_alu32,b3_32=>b_alu32,cin=>"0",sub=>"1",sum_32=>o1,cout=>c1,ov=>ov1);
adder32 port map(a3_32=>a_alu32,b3_32=>b_alu32,cin=>"0",sub=>"0",sum_32=>o2,cout=>c2,ov=>ov2);
end Behavioral;
错误按摩: 错误:HDLC编译器:374第37行:实体尚未编译。
错误:HDLCompiler:69第40行:未声明。
错误:HDLCompiler:69第41行:未声明。
错误:HDLCompiler:69第42行:未声明。
错误:HDLCompiler:69第43行:未声明。
错误:HDLCompiler:69第45行:未声明。
错误:HDLCompiler:69第46行:未声明。
错误:HDLCompiler:69第47行:未声明。
错误:HDLCompiler:69第50行:未声明。
错误:HDLCompiler:69第51行:未声明。
错误:HDLCompiler:69第52行:未声明。
错误:HDLCompiler:69第53行:未声明。
错误:HDLCompiler:69第54行:未声明。
错误:HDLCompiler:69第55行:未声明。
错误:HDLCompiler:806第58行:“port”附近的语法错误。
错误:HDLCompiler:806第59行:“;”附近的语法错误。
答案 0 :(得分:0)
根据定义,ALU有两个数据输入:a
和b
,功能代码输入,状态输出以及结果输出。这将导致像
entity alu is
generic
(
width : integer
);
port
(
a : in std_logic_vector(width - 1 downto 0);
b : in std_logic_vector(width - 1 downto 0);
fc : in fc_t;
status : out sc_t;
result : out std_logic_vector(width downto 0)
);
(看起来与你的完全不同)。
除此之外,您还需要两种枚举类型来编码状态和功能代码:
type fc_t is (fc_add, fc_add, fc_shift, fc_compare);
type sc_t is (sc_ne, sc_eq, sc_err);
我会把建筑留给你(你已经拥有了大部分建筑,你只需要把它放到正确的地方)。