Question

在顶层模块中，有两个输入i1(3 downto 0)和i2(3 downto 0)，它们将降低组件，从而再次转向另一个较低的组件。在进行一些操作后，我们从内存单元获取data_o(3 downto 0)的输出。现在我的问题是如何将此data_o与i2相关联，以便下次我们只输入一个输入，即i1。 i2值将被视为先前的状态data_o值，并使用此数据进行迭代。

我用VHDL编写了这段代码：

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;


entity top_Module is
  port (
    i1 : in std_logic_vector(3 downto 0);
    i2 : in std_logic_vector(3 downto 0);
    f1 : in std_logic_vector(3 downto 0);
    f2 : in std_logic_vector(3 downto 0);
    f3 : in std_logic_vector(3 downto 0);
    f4 : in std_logic_vector(3 downto 0);

    start : in std_logic;
    ctrl  : in std_logic_vector(3 downto 0);
    sel   : in std_logic_vector(1 downto 0);
    clk   : in std_logic;

    address : in integer;
    rst     : in std_logic;

    --two main output.
    data_o : out std_logic_vector(3 downto 0);
    ca   : out std_logic;

    --fault indication.
    d_err      : out std_logic;
    cid_0      : out std_logic;
    cid_1      : out std_logic
    );
end top_Module;


architecture error_free of top_Module is

  component TMR_Module
    port (
      i1 : in std_logic_vector(3 downto 0);
      i2 : in std_logic_vector(3 downto 0);
      f1 : in std_logic_vector(3 downto 0);
      f2 : in std_logic_vector(3 downto 0);
      f3 : in std_logic_vector(3 downto 0);

      start : in  std_logic;
      ctrl  : in  std_logic_vector(3 downto 0);
      sel   : in  std_logic_vector(1 downto 0);
      clk   : in  std_logic;
      --two main output y and ca;
      y     : out std_logic_vector(3 downto 0);
      ca  : out std_logic;

      d_err : out std_logic;
      cid_0 : out std_logic;
      cid_1 : out std_logic);
  end component;

  type ram_t is array (0 to 255) of std_logic_vector(3 downto 0);
  signal z    : std_logic_vector(3 downto 0);
  signal z1   : std_logic_vector(3 downto 0);
  signal ram  : ram_t := (others => (others => '0'));

begin

  x1 : TMR_Module port map(i1,
                           i2,
                           f1,
                           f2,
                           f3,
                           start,
                           ctrl,
                           sel,
                           clk,
                           z,
                           ca,
                           d_err,
                           cid_0,
                           cid_1
                           );

  process(Clk)
    variable data_i : std_logic_vector(3 downto 0);
    variable i      :std_logic_vector(3 downto 0);
  begin
    z1         <= z or f4;
    if(rst = '1') then
      data_o <= ram(address);
    elsif(rising_edge(Clk))then
      if(f4 = "0000") then
        data_i       := z1;
        ram(address) <= data_i;
        i            := ram(address);
      else
        i := ram(address);
      end if;
      data_o <= i;
    end if;
  end process;

end error_free;

现在如何将data_o或ram(address)值分配给i2，以便下次我只能提供i1输入，data_o将从i1生成{1}}和i2 <= data_o。

Answer 1

简单的方法是将'data_o'循环回到i2之外 top_Module，因此不需要对其进行任何修改 top_Module本身，如果top_Module不是最终的顶部。

然后代码就像：

i2_or_data <= i2 when (use_i2_not_data = '1') else data_o;

i2_or_data是一个连接到i2端口的新信号 top_Module，而use_i2_not_data是一个新的信号，可以控制是否有在迭代中使用原始i2或data_o。

如果top_Module是设备中的最后一个，那么i2之间的选择 data_o可以在top_Module内部完成。这个代码可能是：

  -- Signals for selection between i2 and data_o as i2 port for TMR_Module
  signal data_o_sig      : std_logic_vector(3 downto 0);  -- Internal signal for internal use also
  signal use_i2_not_data : std_logic;                     -- Select between i2 ('1') or data_o ('0')
  signal i2_or_data      : std_logic_vector(3 downto 0);  -- i2 or data_o value

begin

  i2_or_data <= i2 when (use_i2_not_data = '1') else data_o_sig;

  x1 : TMR_Module port map(i1,
                           i2_or_data,
  ...
                           );

  process(Clk)
    variable data_i : std_logic_vector(3 downto 0);
  begin
    z1         <= z or f4;
    d_err_buff <= z1(0) and z1(1) and z1(2) and z1(3);
    if(rst = '1') then
      data_o_sig <= ram(address);  -- Drive internal data_o_sig to allow internal use
    elsif(rising_edge(Clk))then
      if(f4 = "0000") then
        data_i       := z1;
        ram(address) <= data_i;
        i            <= ram(address);
      else
        i <= ram(address);
      end if;
      data_o_sig <= i;  -- Drive internal data_o_sig to allow internal use
    end if;
  end process;

  data_o <= data_o_sig;  -- Drive output port from internal signal
  ...

因为使用VHDL-2002及更早版本，因此需要使用内部data_o_sig 然后，无法在模块中读取输出端口。

除上述之外，控制信号use_i2_not_data必须是使用i2或data_o的条件驱动。

如何将输出端口连接到输入端口

1 个答案: