Question

我想知道如何通过信号连接一个模块，输入端口到输出端口。

我想在标题为“rs422_top”的组件中连接rx422_i。模块到tx422_o。我使用信号＆＃39; tx422＆＃39;在港口之间架起桥梁。

但是，这会产生一个综合错误，表明＆＃39; tx422_o＆＃39;有多个司机。

你知道如何解决这个问题吗？

我的代码是：

entity nsgcc_top_rs422 is    
 port (
...
      rx422_i                 : in  std_logic;
      tx422_o                 : out std_logic;
...
);
end nsgcc_top_rs422

signal tx422 : std_logic;

tx422 <= rx422_i;
tx422_o <= tx422;


rs422_inst : rs422_top
 port map (
...
      rx422_i                   => tx422,
      tx422_o                   => tx422,
...
);

Answer 1

Here's an actual MCVe based on your code:

onBeaconsDiscovered

And it gives a conflict that actually shows up in nsgcc_rs422_top:

Both the input and output to bottom level component rs422_top are 'X'.

Connecting an input to an output:

library ieee;
use ieee.std_logic_1164.all;

entity rs422_top is
    port (
        rx422_i:    in  std_logic;
        tx422_o:    out std_logic
    );
end entity;

architecture foo of rs422_top is
begin
    tx422_o <= not rx422_i after 1 ns;
end architecture;

library ieee;
use ieee.std_logic_1164.all;

entity nsgcc_top_rs422 is    
 port (
      rx422_i:          in  std_logic;
      tx422_o:          out std_logic
);
end nsgcc_top_rs422;

architecture fum of nsgcc_top_rs422 is
    component rs422_top
        port (
        rx422_i:    in  std_logic;
        tx422_o:    out std_logic
        );
    end component;

    signal tx422:  std_logic; 

begin

    tx422 <= rx422_i;
    tx422_o <= tx422;

rs422_inst:  
    rs422_top
        port map (
            rx422_i => tx422,
            tx422_o => tx422
        );
end architecture;

library ieee;
use ieee.std_logic_1164.all;

entity nsgcc_top_rs422_tb is
end entity;

architecture foo of nsgcc_top_rs422_tb is
    signal rx422_i: std_logic;
    signal tx422_o: std_logic;
begin
DUT:
    entity work.nsgcc_top_rs422
        port map (
            rx422_i => rx422_i,
            tx422_o => tx422_o
        );
STIMULIS:
    process
    begin
        wait for 10 ns;
        rx422_i <= '0';
        wait for 10 ns;
        rx422_i <= '1';
        wait for 10 ns;
        wait;
    end process;
end architecture;

gives:

Which reduces the signal net to one driver (and doesn't connect the rs422_top input to it's output).

如何通过VHDL中的信号将输入端口连接到一个模块中的输出端口

1 个答案: