Question

我的vhdl代码如下：

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;


ENTITY pc IS PORT(
d   : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
clk : IN STD_LOGIC; -- clock.
q   : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) -- output
);
END pc;

ARCHITECTURE description OF pc IS
BEGIN
process(clk)
begin
    if rising_edge(clk) then
            q <= d;
    else
             q <= x"00000000";
    end if;
end process;
END description;


library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity ins_memory is
port( inp1 : in std_logic_vector(31 downto 0);
  oup1 : out std_logic_vector (4 downto 0);
  clk : in std_logic);
end ins_memory;

architecture behv1 of ins_memory is
type ROM_Array is array (0 to 14)
of std_logic_vector(4 downto 0);
constant Content: ROM_Array := (
0 => "00001",
-- Suppose ROM has
1 => "00010",
-- prestored value
2 => "00011",
-- like this table
3 => "00100",
--
4 => "00101",
--
5 => "00110",
--
6 => "00111",
--
7 => "01000",
--
8 => "01001",
--
9 => "01010",
--
10 => "01011",
--
11 => "01100",
--
12 => "01101",
--
13 => "01110",
--
14 => "01111",
--
OTHERS => "11111"
--
);

component pc IS PORT(
d   : IN STD_LOGIC_VECTOR(31 DOWNTO 0) :=x"00000000";
clk : IN STD_LOGIC; -- clock.
q   : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END component;

begin
D1: pc port map(q=> inp1,clk=>clk,d=>open);
process(inp1,clk)
begin
oup1<= Content (conv_integer(inp1));
end process;

end behv1;

基本上，我试图将'signal q'连接到实体pc的输出'signal inp1'，这是实体ins_memory的输入，但是当我以简单的方式尝试它时我得到了跟随错误

D1：pc端口映射（q =＆gt; inp1，clk =＆gt; clk，d =＆gt; open）; 更新端口BEHV1：不允许IN模式IN的INP1。请验证端口映射是否正确。

Answer 1

inp1端口是顶级实体（memory）的输入，您尝试将其连接到输出内部组件（pc）。所以它将从两个方向驱动 - 从顶层模块的外部和这个内部组件。这显然是非法的。

如何将一个实体的输出与其他实体的输入连接起来

1 个答案: