Question

代码很简单，有一堆ifs在变量BUS中放一定值，模拟时的问题，BUS输出等于：zzzzzzzzzzzzzzzz 虽然它应该具有与if情况相对应的某些值。

module Bus (AR_OUT, IR_OUT, DR_OUT, PC_OUT, AC_OUT, MEM_OUT, read, S, BUS);

 input [11:0]AR_OUT ;
 input [11:0]PC_OUT ;
 input [15:0]IR_OUT ;
 input [15:0]DR_OUT ;
 input [15:0]AC_OUT ;
 input [15:0]MEM_OUT ;
 input read ;
 input [2:0]S ;

 output [15:0]BUS ;

 reg [15:0]BUS ;
 // inputs are implicitly defined as wire


always @*
   begin

 if(S == 3'b001)
   BUS = AR_OUT;

 else if(S == 3'b010)
   BUS = PC_OUT;  

 else if(S == 3'b011)
   BUS = DR_OUT;

 else if(S == 3'b100)
   BUS = AC_OUT;

 else if(S == 3'b101)
   BUS = IR_OUT;

 else if( (S == 3'b111)&&(read == 1'b1) )
   BUS = MEM_OUT;

 else 
   BUS = 16'b 0000000000000000; 
 end

endmodule

module Bus_tb();

 reg [11:0]AR_OUT ;
 reg [11:0]PC_OUT ;
 reg [15:0]IR_OUT ;
 reg [15:0]DR_OUT ;
 reg [15:0]AC_OUT ;
 reg [15:0]MEM_OUT ;
 reg read ;
 reg [2:0]S ;

 wire [15:0]BUS ;

 initial begin

 AR_OUT = 12'b 0000_0000_1111 ;  
 PC_OUT = 12'b 0000_1111_0000 ;
 IR_OUT = 16'b 0000_0000_1111_0000 ;
 DR_OUT = 16'b 0000_0000_1111_1111 ;
 AC_OUT = 16'b 0000_1111_1111_0000 ;
 MEM_OUT = 16'b 1111_0000_1111_0000 ;

 S = 3'b 001 ;
 #10 S = 3'b 011;
 #10 S = 3'b 010;
 #10 S = 3'b 000;   // 
 #10 S = 3'b 101;
 #10 S = 3'b 100;
 #10 S = 3'b 111;
 #5 read = 1'b1;


 end
 endmodule

Answer 1

您的Bus模块未在Bus_tb测试平台中实例化。您需要实例化Bus的实例并连接端口。

E.g。：

Bus u_bus( .BUS(BUS), ...);

Answer 2

为什么使用模块Bus_tb？为什么不使用案例结构？试试这个：

module Bus(AR_OUT, IR_OUT, DR_OUT, PC_OUT, AC_OUT, MEM_OUT, read, S, BUS);

 input [11:0]AR_OUT ;
 input [11:0]PC_OUT ;
 input [15:0]IR_OUT ;
 input [15:0]DR_OUT ;
 input [15:0]AC_OUT ;
 input [15:0]MEM_OUT ;
 input read ;
 input [2:0]S ;
 output [15:0]BUS ; 
 reg [15:0]BUS ;
 // inputs are implicitly defined as wire


always @(S or AR_OUT or IR_OUT or DR_OUT or PC_OUT or AC_OUT or MEM_OUT or read)
case(S)
1:BUS = AR_OUT;
2:BUS = PC_OUT;
3:BUS = DR_OUT;
4:BUS = AC_OUT;
5:BUS = IR_OUT;
7:if(read) BUS = MEM_OUT; //there is no state 6 in your code
default BUS = 16'b0000000000000000;
endcase

endmodule

在Verilog中模拟输出等于zzzzzz

2 个答案: