在输出IR REGISTER = XXXXX中获取XXX

时间:2015-10-01 23:48:13

标签: verilog

我的目标是将数据作为输入并将其存储在内存中我将其存储在Fetch_Memory中以及稍后我为每个时钟边沿递增pC值,我正在从内存中进行异步读取各自的价值。

  input clk;
    input [31:0] din;
    input reset;
    reg [31:0] PC = 31'b0;
    output reg [31:0] IR;

    integer counter = 512'b0; 
    parameter data_width = 32;
    parameter data_depth = 512;


  always @(posedge clk)
    begin 
        if(reset)
        begin 
            counter <= 512'b0;
            PC <= 32'd0;
    //      IR <= 32'd0;

        end
        else 
        begin 
        Fetch_Memory[PC] <= din;//din;
        counter <= counter + 512'h1;
        PC <= PC + 32'd1;  //32'h00000001;
    //  IR <= Fetch_Memory[counter];

        end

    end

    always @(posedge reset)
    begin 
        IR <= 32'b0;
    end
**//   thE PROBLEM IS iN HERE i AM gETIING xxxx VALUES IN THE IR REGISTER**
    always @(PC)
    begin 
        IR = Fetch_Memory[PC];

    end

    endmodule






   *`Here I am ADDING TH**E tEST BENCH TOO**`**     
parameter data_depth = 512;
parameter data_width = 32;
    // Inputs
    reg clk;
    reg [31:0] din;
    reg [31:0] PC;
    reg reset;

// Outputs
reg [31:0] IR;
integer counter ;
reg [data_width-1:0] Fetch_Memory [data_depth-1:0];

     always 
     begin 
     #5 clk = ~clk;


     end

        initial begin
            // Initialize Inputs
            #0 reset = 1;
            #15 reset =0;
            clk = 1'b0;
            din = 32'h25645878;

            // Wait 100 ns for global reset to finish
            #100;

            // Add stimulus here
    end

1 个答案:

答案 0 :(得分:0)

您将IR设置为两个始终块,这在综合中是不可能的,坐不会为硬件组件建模。

always @(posedge reset)
    begin
        IR <= 32'b0;
    end
**//   thE PROBLEM IS iN HERE i AM gETIING xxxx VALUES IN THE IR REGISTER**
    always @(PC)
    begin
        IR = Fetch_Memory[PC];

    end

对于组合(异步)查找,只需使用:

always @* begin
  IR = Fetch_Memory[PC];
end

如果IR仍为X,则必须将数据写入Fetch_Memory。