Question

这里是示例1。

   module my_fsm(clk, reset, X, Y, Z);
     input clk, reset, X;
     output Y, Z;
   endmodule

这是示例2。

module my_fsm(clk, reset, X, Y, Z);
 input clk, reset, X;
 output logic Y, Z;
endmodule

如您所见，有输出Y，Z和输出逻辑Y，Z。 Verilog中输出和输出逻辑之间的根本区别是什么？

Answer 1

在系统verilog中引入了

logic关键字。它避免了reg和wire之间的混淆。

input a;
output reg x; //x is declared as a register
always@(posedge clk)
 x <= a;

在块上方书写的另一种方式

input a;
output logic x; //Here x is taken as a register since its used inside always block
always@(posedge clk)
x <= a;

input a;
output logic x;
assign x = a; //Here x is taken as a wire due to assign statement

Verilog中的输出逻辑和输出逻辑有什么区别？

1 个答案: