这是我想要实现的架构。但是在模拟测试平台期间我在modelsim中遇到错误,但我的编译成功了。
# ** Error: (vsim-3053) C:/altera/81/modelsim_ae/examples/matrix_generation_unit.v(8): Illegal output or inout port connection (port 'q').
# Region: /mgu_tb/m1/a1
# ** Error: (vsim-3053) C:/altera/81/modelsim_ae/examples/matrix_generation_unit.v(10): Illegal output or inout port connection (port 'q').
# Region: /mgu_tb/m1/a3
# ** Error: (vsim-3053) C:/altera/81/modelsim_ae/examples/matrix_generation_unit.v(12): Illegal output or inout port connection (port 'q').
# Region: /mgu_tb/m1/a5
# ** Error: (vsim-3053) C:/altera/81/modelsim_ae/examples/matrix_generation_unit.v(14): Illegal output or inout port connection (port 'q').
# Region: /mgu_tb/m1/a7
主要模块:
module mgu(in,clk,rst,c0,c1,c2,c3);
//module mgu(in,clk,rst);
input in,clk,rst;
output reg c0,c1,c2,c3;
//reg c0,c1,c2,c3;
wire w1,w2,w3;
dff a1 (.clk(clk),.rst(rst),.din(in),.q(c0));
xor a2 (w1,c0,c1);
dff a3 (clk,rst,w1,c1);
xor a4 (w2,c1,c2);
dff a5 (clk,rst,w2,c2);
xor a6 (w3,c2,c3);
dff a7 (clk,rst,w3,c3);
endmodule
D翻转翻牌
module dff (clk,rst,din,q);
input clk,din,rst;
output reg q;
always @ ( posedge clk)
begin
if (rst)
q<=1'b0;
else
q<=din;
end
endmodule
测试台
module mgu_tb( );
reg in,clk,rst;
wire c0,c1,c2,c3;
mgu m1(in,clk,rst,c0,c1,c2,c3);
initial
begin
clk = 1'b0;
rst = 1'b1;
in = 1'b0;
end
always #5 clk = ~clk;
initial
begin
#10 rst = 1'b0;
#10 in = 1'b1;
#10 in = 1'b1;
#10 in = 1'b1;
#10 in = 1'b1;
#10 in = 1'b1;
#10 in = 1'b1;
#10 in = 1'b1;
#10 in = 1'b1;
#10 in = 1'b1;
#10 in = 1'b1;
end
endmodule
答案 0 :(得分:0)
无需使用&#34; output reg
&#34;在主模块输出端口。只是&#34; output
&#34;独自工作。