Question

这是我的64位乘法器的完整代码。它在full_multiplier第17行给出错误，我已经鼓起勇气（3星）。错误是vsim-3053端口'out2'的非法输出或inout端口连接。

 module full_multiplier(input [63:0] a, b, input [1:0] select, input clk, output reg [63:0] out);

        wire [10:0] exp;
        wire state;
        wire out1;
        wire [51:0] man;
        wire sign;



            check_zero ch1( a, b, 2'b10, clk,state);    
            check_sign c1(sign,a,b,clk,state);      
        addexp a1(exp, a, b,clk,state);            
        mul1 m1( man, a, b, clk,state);         

        **normalize n1(out, sign, exp, man, clk);**


    endmodule


    module check_zero (input [63:0] a, b, input [1:0] select, input clk,  output reg state);

    parameter done = 1'b0, next= 1'b1;


    always @(posedge clk) begin
    if ((a[51:0] == 0) && (b[51:0] == 0)) begin  
              //out <= 64'b0;
              state <= done;

    end else if (a[51:0]==0 && select==0) begin
        //  out <= b;
              state <= done;
    end else if (b[51:0]==0 && select==0) begin
        //  out <= a;
              state <= done;

    end else if (a[51:0]==0 && select==1) begin
        //  out[63] <= ~b[63];
        //  out[62:0] <= ~b[62:0];
              state <= done;
    end else if (b[51:0]==0 && select==1) begin
        //  out <= a;
              state <= done;

    end else if (a[51:0]==0 && select==2) begin
        //  out <= 0;
              state <= done;
    end else if (b[51:0]==0 && select==2) begin
        //  out <= 0;
              state <= done;

    end else if (a[51:0]==0 && select==3) begin
        //  out <= 0;
              state <= done;
    end else if (b[51:0]==0 && select==3) begin
        //    out[63] <= 1;
            //    out[62:52] <= 2047;
            //    out[51] <= 1;
            //    out[50:0] <= 0;
                state <= done;
    end else begin
        state<=next;
    end
    end
    endmodule

    module check_sign(output reg sign,
            input [63:0]   x,
            input [63:0]   y,
        input clk,
        input state);

    always@ (posedge clk) begin
    if (state==1) begin

    sign <= y[63] ^ x[63];

    end else begin
    sign =0;
    end
    end
    endmodule

    module addexp(output reg [10:0] exp,
            input [63:0]   x,
            input [63:0]   y,
        input clk,
        input state);

    always@ (posedge clk) begin
    if (state==1) begin

    exp <= x[62:52] + y[62:52]- 1023;

    end else begin
    exp <=1023;
    end
    end
    endmodule

    module mul1(
            output reg [51:0]  c,
    //  output reg [7:0] addexp,
            input [63:0]   x,
            input [63:0]   y,
        input clk,
        input state); 

    reg [103:0] p;
    reg [103:0]a;
    integer i;

    always @(posedge clk) begin
    if (state==1) begin
      a=x;
      p=0; // needs to zeroed
      for(i=0;i<51;i=i+1) begin
        if(y[i]) begin
          p=p+a; // must be a blocking assignment
        end
        a=a<<1;
      end

      for(i=103;i>=0;i=i-1) begin
        if (p[i]) begin
          c=p[i+:52]; 
        //  addexp=i-51;
         p=0;
        end
       end
    end else begin
     c=0;
    end
    end
    endmodule


    module normalize(output reg [63:0] out2,
            input    sign,
            input [10:0]   exp,
        input [51:0] man,
        input clk);

    always@ (posedge clk) begin

    out2 <= {sign,exp,man};
    end
    endmodule

module tb_mul1;

reg [63:0] a;

reg [63:0] b;
reg clk;
wire [63:0] out;

full_multiplier m1 ( a, b,2'b10, clk, out);

initial #200 $finish;
initial begin clk=0; forever #5 clk=~clk; end

initial begin

    a = 64'h000_0_0000_0000_0000;
    b = 64'h000_0_0000_0000_0000;
    #20;

    #20;
    b = 64'h080_8_0000_0000_0001;
    a = 64'h080_F_FFFF_FFFF_FFFF;
    #60 b = 64'h080_8_0000_0000_0003;
    #60 b = 64'h081_8_0000_0000_0000;
    #60 a = 64'h080_8_0000_0040_0000;
    #60 b = 64'h090_8_0000_0000_0001;
    #60 a = 64'h880_8_0000_0040_0000;
    #60 a = 64'h890_8_0000_0040_0000;
    #60 a = 64'h890_8_0000_0000_0001;
    #60 b = 64'h890_8_0000_0000_0001;
    #60 b = 64'h890_1_0000_0000_0000;


    #60 $stop;
end


endmodule

Answer 1

在您的顶级模块中，您已声明信号为reg：

module full_multiplier(input [63:0] a, b, input [1:0] select, input clk, output reg [63:0] out);

这似乎是因为您曾经在该模块中分配该信号。现在，您将从normalize的输出端口获取该信号的值。这意味着现在应该只使用电线而不是电子邮件。如果您将模块更改为（删除reg）：

module full_multiplier(input [63:0] a, b, input [1:0] select, input clk, output [63:0] out);

然后它应该编译。

Model Sim verilog error端口'out2'的非法输出或inout端口连接

1 个答案: