我收到错误：端口＆＃39; final_result＆＃39;非法输出或inout端口连接

Question

每次运行此代码时，都会出现关于final_result的错误。我是verilog的新手，我似乎无法找到解决方案。我已将final_result声明为输出，这应该足够了。

module chip (CLK, RESET,t_m, A, B, final_result);

   input CLK, RESET, t_m;
   input [7:0] A, B;
   output [15:0] final_result;

   wire [7:0]    a1, b1, r1, r2;
   wire [15:0]   mult_result;
   wire [15:0]   signature;
   wire [15:0] final_result;


   lfsr16 lfsr16_0 (.clk(CLK), .reset(RESET), .a(a1), .b(b1));

   mux  mux_0 ( .D_0(A), .D_1(a1), .select(t_m), .mux_out (r1));
   mux  mux_1 ( .D_0(B), .D_1(b1), .select(t_m), .mux_out (r2));

   mult mult_0 (.clk(CLK), .reset(RESET), .A(r1), .B(r2), .result(mult_result));

   sa16 sig_analyzer16(.clk(CLK), .reset(RESET), .in(mult_result), .out(signature));

   mux1  mux_2 ( .D_0(mult_result), .D_1(signature), .select(t_m), .mux_out(final_result));

endmodule // chip

mux1已声明为：

 module  mux1( D_0 , D_1,select,mux_out);

 input [15:0] D_0, D_1;
 input select ;
 output [15:0] mux_out;
  //wire  [15:0] mux_out;

 assign mux_out = (select) ? D_0 : D_1;

endmodule