Question

我点击了以下链接，但无法更正错误。

Verilog HDL Port Connection error 我正在尝试在Quartus中编译verilog代码，但是会抛出Error。

Counter_Top_Module.v（12）的Vererilog HDL端口连接错误：必须将输出或inout端口“ out”连接到结构网络表达式

import java.sql.Connection;
import java.sql.DriverManager;
import java.sql.ResultSet;
import java.sql.Statement;
public class Test {
    public static Connection connection;
    public void createConnection()
    {
        try {
            if (connection==null) {
                Class.forName("org.postgresql.Driver");
                connection = DriverManager.getConnection("jdbc:postgresql://localhost:5432/abc", "abc", "Welcome");
                connection.setSchema("iiv_location");
            }
        } catch (Exception e) {
            e.printStackTrace();
            System.err.println(e.getClass().getName() + ": " + e.getMessage());
        }
    }

   public static void main(String[] args) {
        try {
            test object = new test();
            object.createConnection();
            Statement statement = connection.createStatement();
            ResultSet resultSet = statement.executeQuery("select iiv_prescan_invoice_details.deadline_date from iiv_prescan_invoice_details");
            while (resultSet.next()) {
                System.out.println(resultSet.getString("deadline_date"));
           }
        } catch (Exception e) {
            e.printStackTrace();
        }
   }
}

SUB-FUNCTION

module Counter_Top_Module // TOP FUNCTION
(
 input wire clk_50,
 output reg[7:0] data                           
); 
counter Testing                  // SUB-FUNCTION
(
 .clk                 (clk_50),
 .out                 (data[7:0])
);  

SPI Component                  //// SUB-FUNCTION
 (
.clk_clk                                   (clk_50),  
.pio_out_external_connection_export        (data[7:0])
  );
endmodule

Verilog HDL端口连接错误：必须将输出或输入端口“ xxx”连接到结构网络表达式

0 个答案: