Question

我想将以下VHDL代码转换为Verilog。但是我遇到了一些我在这里提到的问题compilation error。有人可以给我一些关于如何在Verilog中正确编写相同函数的提示吗？

谢谢！

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.classic_multiplier_parameters.all;
entity poly_multiplier is
port (
  a, b: in std_logic_vector(M-1 downto 0);
  d: out std_logic_vector(2*M-2 downto 0)
);
end poly_multiplier;


architecture simple of poly_multiplier is
  type matrix_ands is array (0 to 2*M-2) of STD_LOGIC_VECTOR(2*M-2 downto 0);
  signal a_by_b: matrix_ands;
  signal c: std_logic_vector(2*M-2 downto 0);
begin

  gen_ands: for k in 0 to M-1 generate
    l1: for i in 0 to k generate
       a_by_b(k)(i) <= A(i) and B(k-i);
    end generate;
  end generate;

  gen_ands2: for k in M to 2*M-2 generate
    l2: for i in k to 2*M-2 generate
       a_by_b(k)(i) <= A(k-i+(M-1)) and B(i-(M-1));
    end generate;
  end generate;

  d(0) <= a_by_b(0)(0);
  gen_xors: for k in 1 to 2*M-2 generate
    l3: process(a_by_b(k),c(k))
        variable aux: std_logic;
        begin
        if (k < M) then
          aux := a_by_b(k)(0);
          for i in 1 to k loop aux := a_by_b(k)(i) xor aux; end loop;
        else
          aux := a_by_b(k)(k);
          for i in k+1 to 2*M-2 loop aux := a_by_b(k)(i) xor aux; end loop;
        end if;
        d(k) <= aux;
    end process;
  end generate;

end simple;

Answer 1

下面的代码部分应该这样做。注意：

在你的代码中，常量M被定义为一个单独的包，我把它移动为参数（Verilog）或泛型（VHDL）
Verilog区分大小写，因此您必须修复M，a和b的拼写

Verilog代码：

module poly_multiplier(a, b, d);

   parameter M = 0;

   input [M - 1:0] a;
   input [M - 1:0] b;
   output [2 * M - 2:0] d;

   wire [M - 1:0]       a;
   wire [M - 1:0]       b;
   reg [2 * M - 2:0]    d;

   wire [2 * M - 2:0]   a_by_b[0:2 * M - 2];
   wire [2 * M - 2:0]   c;

   generate
      genvar            k0;
      for (k0 = 0; k0 <= M - 1; k0=k0+1) begin : gen_ands
         genvar i0;
         for (i0 = 0; i0 <= k0; i0=i0+1) begin : l1
            assign a_by_b[k0][i0] = a[i0] & b[k0 - i0];
         end
      end
   endgenerate

   generate
      genvar k1;
      for (k1 = M; k1 <= 2 * M - 2; k1=k1+1) begin : gen_ands2
         genvar i1;
         for (i1 = k1; i1 <= 2 * M - 2; i1=i1+1) begin : l2
            assign a_by_b[k1][i1] = a[k1 - i1 + M - 1] & b[i1 - M + 1];
         end
      end
   endgenerate

   always @(*) begin
      d[0] = a_by_b[0][0];
   end

   generate
      genvar k2;
      for (k2 = 1; k2 <= 2 * M - 2; k2=k2+1) begin : gen_xors
         reg  aux;
         integer i;
         always @(*) begin : P2

            if ((k2 < M)) begin
               aux = a_by_b[k2][0];
               for(i = 1; i <= k2; i = i + 1) begin
                  aux = a_by_b[k2][i] ^ aux;
               end
            end
            else begin
               aux = a_by_b[k2][k2];
               for(i = k2 + 1; i <= 2 * M - 2; i = i + 1) begin
                  aux = a_by_b[k2][i] ^ aux;
               end
            end
            d[k2] = aux;
         end

   end
   endgenerate
endmodule

VHDL转换为verilog

1 个答案: