我需要从verilog到vhdl编写一些代码。我需要重写的代码是de2-115 fpga上的摄像头。我错了什么？
这是Altera的verilog代码。我编辑了一下来测试一些东西。但它仍然有效。我不明白为什么这段代码确实有两个具有相同条件的if语句。我试过它，如果它不起作用。在VHDL代码中，我还尝试了一个和两个if语句，其中reset =＆＃39; 0＆＃39;条件，但它仍然不起作用。
module I2C_Controller (
CLOCK,
I2C_SCLK,//I2C CLOCK
I2C_SDAT,//I2C DATA
I2C_DATA,//DATA:[SLAVE_ADDR,SUB_ADDR,DATA]
GO, //GO transfor
EEND, //END transfor
W_R, //W_R
ACK, //ACK
RESET
);
input CLOCK;
input [31:0]I2C_DATA;
input GO;
input RESET;
input W_R;
inout I2C_SDAT;
output I2C_SCLK;
output EEND;
output ACK;
reg SDO;
reg SCLK;
reg EEND;
reg [31:0]SD;
reg [6:0]SD_COUNTER;
wire I2C_SCLK=SCLK | ( ((SD_COUNTER >= 4) & (SD_COUNTER <=39))? ~CLOCK :0 );
wire I2C_SDAT=SDO?1'bz:0 ;
reg ACK1;
wire ACK=ACK1;
//--I2C COUNTER
always @(negedge RESET or posedge CLOCK ) begin
if (!RESET) SD_COUNTER=6'b111111;
else begin
if (GO==0)
SD_COUNTER=0;
else
if (SD_COUNTER < 41) SD_COUNTER=SD_COUNTER+1;
end
if (!RESET) begin SCLK=1;SDO=1; ACK1=0; EEND=1; end
else
case (SD_COUNTER)
6'd0 : begin ACK1=0 ; EEND=0; SDO=1; SCLK=1;end
//start
6'd1 : begin SD=I2C_DATA;SDO=0;end
6'd2 : SCLK=0;
//SLAVE ADDR
6'd3 : SDO=SD[31];
6'd4 : SDO=SD[30];
6'd5 : SDO=SD[29];
6'd6 : SDO=SD[28];
6'd7 : SDO=SD[27];
6'd8 : SDO=SD[26];
6'd9 : SDO=SD[25];
6'd10 : SDO=SD[24];
6'd11 : SDO=1'b1;//ACK
//SUB ADDR
6'd12 : begin SDO=SD[23]; ACK1=I2C_SDAT; end
6'd13 : SDO=SD[22];
6'd14 : SDO=SD[21];
6'd15 : SDO=SD[20];
6'd16 : SDO=SD[19];
6'd17 : SDO=SD[18];
6'd18 : SDO=SD[17];
6'd19 : SDO=SD[16];
6'd20 : SDO=1'b1;//ACK
//DATA
6'd21 : begin SDO=SD[15]; ACK1=I2C_SDAT; end
6'd22 : SDO=SD[14];
6'd23 : SDO=SD[13];
6'd24 : SDO=SD[12];
6'd25 : SDO=SD[11];
6'd26 : SDO=SD[10];
6'd27 : SDO=SD[9];
6'd28 : SDO=SD[8];
6'd29 : SDO=1'b1;//ACK
//DATA
6'd30 : begin SDO=SD[7]; ACK1=I2C_SDAT; end
6'd31 : SDO=SD[6];
6'd32 : SDO=SD[5];
6'd33 : SDO=SD[4];
6'd34 : SDO=SD[3];
6'd35 : SDO=SD[2];
6'd36 : SDO=SD[1];
6'd37 : SDO=SD[0];
6'd38 : SDO=1'b1;//ACK
//stop
6'd39 : begin SDO=1'b0; SCLK=1'b0; ACK1=I2C_SDAT; end
6'd40 : SCLK=1'b1;
6'd41 : begin SDO=1'b1; EEND=1; end
endcase
end
endmodule
这是VHDL代码：
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
entity II2C_Controller is
PORT
(
CLOCK : in std_logic;
I2C_SCLK : out std_logic;
I2C_SDAT : inout std_logic;
I2C_DATA : in std_logic_vector(31 downto 0);
GO : in std_logic;
EEND : out std_logic;
W_R : in std_logic;
ACK : out std_logic;
RESET : in std_logic
);
end entity II2C_Controller;
architecture arch_i2c of II2C_Controller is
begin
pclk : PROCESS(CLOCK, RESET)
variable SD_COUNTER : integer;
variable SDO, ACK1, SCLK : std_logic;
variable SD : std_logic_vector(31 downto 0);
begin
if (RESET = '0') then
SD := i2c_DATA;
SD_COUNTER := 127;
elsif(RISing_edge(CLOCK)) then
if(GO = '0') then
SD_COUNTER := 0;
elsif(SD_COUNTER < 41) then
SD_COUNTER := SD_COUNTER + 1;
end if;
end if;
if (RESET = '0') then
SCLK := '1';
SDO := '1';
ACK <= '0';
EEND <= '1';
elsif(rising_edge(CLOCK)) then
ACK <= ACK1;
if SDO = '1' then
I2C_SDAT <= 'Z';
else
I2C_SDAT <= '0'; --Z means pullup
end if;
if(SCLK = '1') then
I2C_SCLK <= SCLK;
elsif(SD_COUNTER >= 4 and SD_COUNTER <=39) then
I2C_SCLK <= not clock;
else
I2C_SCLK <= '0';
end if;
case SD_COUNTER is
when 0 =>
ACK <= '0';
SCLK := '1';
SDO := '1';
EEND <= '0';
when 1 =>
SDO := '0';
when 2 => sclK := '0';
when 3 => SDO := SD(31);
when 4 => SDO := SD(30);
when 5 => SDO := SD(29);
when 6 => SDO := SD(28);
when 7 => SDO := SD(27);
when 8 => SDO := SD(26);
when 9 => SDO := SD(25);
when 10 => SDO := SD(24);
when 11 => SDO := '1';
when 12 => SDO := SD(23);
ACK <= I2c_SDAT;
when 13 => SDO := SD(22);
when 14 => SDO := SD(21);
when 15 => SDO := SD(20);
when 16 => SDO := SD(19);
when 17 => SDO := SD(18);
when 18 => SDO := SD(17);
when 19 => SDO := SD(16);
when 20 => SDO := '1';
when 21 => SDO := SD(15);
ACK <= I2C_SDAT;
when 22 => SDO := SD(14);
when 23 => SDO := SD(13);
when 24 => SDO := SD(12);
when 25 => SDO := SD(11);
when 26 => SDO := SD(10);
when 27 => SDO := SD(9);
when 28 => SDO := SD(8);
when 29 => SDO := '1';
when 30 => SDO := SD(7);
ACK <= I2C_SDAT;
when 31 => SDO := SD(6);
when 32 => SDO := SD(5);
when 33 => SDO := SD(4);
when 34 => SDO := SD(3);
when 35 => SDO := SD(2);
when 36 => SDO := SD(1);
when 37 => SDO := SD(0);
when 38 => SDO := '1';
when 39 => SDO := '0';
SCLK := '0';
ACK <= I2C_SDAT;
when 40 => SCLK := '1';
when 41 => SDO := '1';
EEND <= '1';
when others => NULL;
end case;
end if;
end process;
end architecture arch_i2c;