Question

我在VHDL中定义了以下变量，我需要将它们转换为Verilog。我首先在VHDL中列出变量，然后尝试转换它们：

VHDL代码

constant ValueLoad : std_logic_vector (11*24-1 downto 0) := 
b"0011010_0_0001111_000000000"&
b"0011010_0_0000000_000011111"&
b"0011010_0_0000001_000110111"&
b"0011010_0_0000010_001111001"&
b"0011010_0_0000011_000110000"&
b"0011010_0_0000100_011010010"&
b"0011010_0_0000101_000000001"&
b"0011010_0_0000110_001100010"&
b"0011010_0_0000111_001000011"&
b"0011010_0_0001000_000100000"&
b"0011010_0_0001001_000000001";


signal valueOut : std_logic;

signal registerA : std_logic_vector (11*24-1 downto 0); 
signal divider  : integer;
signal counterA : integer;
signal counterB : integer;

我尝试转换为Verilog

wire valueOut;
wire [11*24-1:0] registerA;
wire divider;
wire counterA;
wire counterB;

这是对的吗？另外，如何在Verilog中定义valueLoad？

Answer 1

这取决于他们的分配方式。如果已分配内部always块，则应为reg或integer个类型。

reg valueOut;
reg [11*24-1:0] registerA;
integer divider;
integer counterA;
integer counterB;

如果通过assign语句分配它们，则它们必须是网络类型。

wire valueOut;
wire [11*24-1:0] registerA;
wire signed [31:0] divider; // 'signed' to allow negative numbers
wire signed [31:0] counterA;
wire signed [31:0] counterB;

VHDL的constant应映射到Verilog的parameter。 VHDL使用&进行污染，Verilog使用大括号污染逗号分隔列表：

parameter [11*24-1:0] ValueLoad = { 
  24'b0011010_0_0001111_000000000,
  24'b0011010_0_0000000_000011111,
  24'b0011010_0_0000001_000110111,
  24'b0011010_0_0000010_001111001,
  24'b0011010_0_0000011_000110000,
  24'b0011010_0_0000100_011010010,
  24'b0011010_0_0000101_000000001,
  24'b0011010_0_0000110_001100010,
  24'b0011010_0_0000111_001000011,
  24'b0011010_0_0001000_000100000,
  24'b0011010_0_0001001_000000001  };

Answer 2

是的，看起来是正确的。这是定义ValueLoad的一种方法：

database

从VHDL到Verilog的数据转换

2 个答案: