Question

我使用4 2x1和--1 1 4x1多路复用器为8x1多路复用器编写代码的方法有什么帮助，这是我独自尝试的代码，但EDA运动场告诉我m1.1 m1.2 m1.4 m1.4和m2没有声明我不知道为什么。是在EDA操场上熟悉VHDL的人，请帮助我完成这项任务？

-这是我到目前为止为使用4 2x1和--1 1 4x1多路复用器的8x1多路复用器尝试的代码，这是VHDL语言的新功能，请有人帮忙吗？ - 图书馆图书馆IEEE; 使用ieee.std_logic_1164.all;

--here is the code that I write for 8x1 multiplexer 
--using 4 2x1 and 1 4x1
entity multiplexer8x1 is   
--declaration for 8x1
port( I : in std_logic_vector(7 downto 0); -- input that need 8x1
      Y: out std_logic; -- output of 8x1 is the output
      s: in std_logic_vector(2 downto 0) is the enable
     );
end multiplexer8x1;

architecture behavior of multiplexer8x1 is
    -- is the component of multiplexer  2x1
    component multiplexer2x1 is 
    --declaration for 2x1
       port( D0,D1: in std_logic; --the output is D0 or D1 
             Y: out std_logic; --is the output 
             s: in std_logic_vector(1 downto 0) -- is the enable multiplexer
            );
     end component;
      -- is the component multiplexer  4x1
      component multiplexer4x1 is 
        --declaration for 4x1
         port( D0 , D1, D2, D3: in std_logic; --the output is D0 or D1 od 
                                              --D2 or D3 
               Y: out std_logic; --is the output 
               s: in std_logic_vector(1 downto 0)--is the enable
              );
end componet;

-- is the output of each 2x1 multiplexer
signal f0,f1,f2,f3 : std_logic; 

begin

--is the 4 2x1 multiplexer output and 4x1 multiplexer
m11: multiplexer2x1 port map(I(0),I(1),f0,Y,s(0),s(1));
m12: multiplexer2x1 port map(I(2),I(3),f1,Y,s(0),s(1));
m13: multiplexer2x1 port map(I(4),I(5),f2,Y,s(0),s(1));
m14: multiplexer2x1 port map(I(6),I(7),f3,Y,s(0),s(1));
m2: multiplexer4x1 port map(f0,f1,f2,f3,Y,s(2));

end behavior;

在EDA操场上使用4个2x1和1个4x1多路复用器的8x1多路复用器

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