在EDA游乐场中使用4个2x1和1个4x1多路复用器创建8x1多路复用器（VHDL语言）

Question

i need to put 4 2x1 multiplexer and 1 4x1 to create a 8x1 multiplexer, 
   this is my code put is has 5 error 
COMP96 ERROR COMP96_0019: "Keyword 'component' expected." "design.vhd" 
COMP96 ERROR COMP96_0015: "')' expected." "testbench.vhd" 
coMP96 ERROR COMP96_0015: "';' expected." "testbench.vhd" 
COMP96 ERROR COMP96_0018: "Identifier expected." "testbench.vhd" 
COMP96 ERROR COMP96_0018: "Identifier expected." "testbench.vhd" 

问题是我不知道如何执行多路复用器的过程，在我的代码中，如您所见，我在8x1多路复用器中编写了2x1和4x1多路复用器的组件，但我不知道如何显示在这些多路复用器中必须执行的过程。请帮助我了解如何使用1个以上的对象创建多路复用器

-- Code your design here
 library IEEE;
 use IEEE.std_logic_1164.all;

entity multiplexer8x1 is   
--declaration for 8x1
 port( I : in std_logic_vector(7 downto 0); -- input that need 8x1
  Y: out std_logic; -- output of 8x1 is the output
  s: in std_logic_vector(2 downto 0) --is the enable
 );
 end multiplexer8x1;
 architecture behavior of multiplexer8x1 is
component multiplexer2x1 is 
--declaration for 2x1
   port( D0,D1: in std_logic; --the output is D0 or D1 
         Y: out std_logic; --is the output 
         s: in std_logic_vector(1 downto 0) -- is the enable multiplexer
        );
 end component;
  -- is the component multiplexer  4x1
  component multiplexer4x1 is 
    --declaration for 4x1
     port( D0 , D1, D2, D3: in std_logic; --the output is D0 or D1 od 
                                          --D2 or D3 
           Y: out std_logic; --is the output 
           s: in std_logic_vector(1 downto 0)--is the enable
          );
 end componet;

 -- is the output of each 2x1 multiplexer
  signal f0,f1,f2,f3 : std_logic; 

  begin

  --is the 4 2x1 multiplexer output and 4x1 multiplexer
  m11: multiplexer2x1 port map(I(0),I(1),f0,Y,s(0),s(1));
   m12: multiplexer2x1 port map(I(2),I(3),f1,Y,s(0),s(1));
  m13: multiplexer2x1 port map(I(4),I(5),f2,Y,s(0),s(1));
  m14: multiplexer2x1 port map(I(6),I(7),f3,Y,s(0),s(1));
  m2: multiplexer4x1 port map(f0,f1,f2,f3,Y,s(2));

  end behavior;

 LIBRARY ieee;
 USE ieee.std_logic_1164.ALL;

  ENTITY multiplexer8x1 IS
 END multiplexer8x1;

 ARCHITECTURE tb OF multiplexer8x1 IS 

COMPONENT multiplexer8x1
port( I : in std_logic_vector(7 downto 0); -- input that need 8x1
  Y: out std_logic; -- output of 8x1 is the output
  s: in std_logic_vector(2 downto 0) is the enable
   );
  END COMPONENT;

  signal f0,f1,f2,f3 : std_logic; 

  BEGIN

 uut: multiplexer8x1 PORT MAP (
      I => I,
      Y => Y,
      S => s,
    ); 

 stim_proc: process
 begin  

s0 <= '0';
s1 <= '0';
s2 <= '0';
wait for 50 ns;

 s0 <= '0';
 s1 <= '0';
 s2 <= '1';
 wait for 50 ns;

 s0 <= '0'; 
 s1 <= '1';
 s2 <= '0';
 wait for 50 ns;

 s0 <= '0';
 s1 <= '1';
 s2 <= '1';
 wait for 50 ns;


 s0 <= '1';
 s1 <= '0';
 s2 <= '0';
 wait for 50 ns;

 s0 <= '1';
 s1 <= '0';
 s2 <= '1';
 wait for 50 ns;

s0 <= '1';
s1 <= '1';
 s2 <= '0';
 wait for 50 ns;

s0 <= '1';
s1 <= '1';
s2 <= '1';
wait for 50 ns;


  end process;

END tb;