如何将测试台的输出固定在波形中？

Question

我正在为4位计数器和测试台编写代码 但是当我在有源HDL中使用波形时;它不显示counter_output，而仅显示“ z”

module first_counter (input clock ,input reset ,output reg [3:0] counter_out); 
 always @(posedge clock or posedge reset ) begin
  if(reset==1'b1)
    counter_out=4'b0000;    
  else                 
    counter_out = counter_out+1;   
 end
endmodule


`timescale 1ps / 1ps
module first_counter_tb;
reg clock;
reg reset;
wire [3:0] counter_out;     
first_counter UUT(.clock(clock),.reset(reset),.counter_out(counter_out));
always  #5 clock = ~clock;                                                                                                                        
initial begin           
  $display ("time\t  clock   reset   counter_out");   
  $monitor($realtime ," ps     %h     %h     %h ",clock,reset,counter_out);  
  clock = 0; 
  reset = 0;    
  #15 reset = 1;
  #180 reset = 0;
  #10 reset = 1;
  #10 $finish;  
end  
endmodule

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