Question

我已经为它编写了一个小的Verilog代码和测试平台。它包含在下面.. 我想将测试平台结果捕获到文件（AA2.txt）。但是，当我运行模拟器时，“结果”显示在监视器上，AA2.txt文件为空。你能帮我弄清楚我错过了什么吗？你能解释一下吗？谢谢。 Bhal Tulpule

    `timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   16:57:34 12/04/2014
// Design Name:   ADC_SAMPLE
// Module Name:   C:/Xilinx131/SOC/SOC501V2/ADC_SAMPLE_tb.v
// Project Name:  SOC501V2
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: ADC_SAMPLE for review with Honeywell
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module ADC_SAMPLE_tb;

    // Inputs
    reg CLK;
    reg ASM_SEL;
    reg [11:0] ADC_BUS;
    reg [7:0] ADC_Wait_Time;

    // Outputs
    wire [7:0] ASM_HB;
    wire [7:0] ASM_LB;
    wire AS_SConv;
    wire AS_OE;
    wire ASM_FLAG;
    wire [3:0] S;

    parameter PERIOD = 100;
    parameter real DUTY_CYCLE = 0.5;
    parameter OFFSET = 0;


    // Instantiate the Unit Under Test (UUT)
    ADC_SAMPLE uut (
        .CLK(CLK), 
        .ASM_SEL(ASM_SEL), 
        .ADC_BUS(ADC_BUS), 
        .ADC_Wait_Time(ADC_Wait_Time), 
        .ASM_HB(ASM_HB), 
        .ASM_LB(ASM_LB), 
        .AS_SConv(AS_SConv), 
        .AS_OE(AS_OE), 
        .ASM_FLAG(ASM_FLAG), 
        .S(S)
    );

    initial begin
        // Initialize Inputs
        CLK = 0;
        ASM_SEL = 1;
        ADC_BUS = 12'hABC;
        ADC_Wait_Time = 4;
    end

   initial    
    begin
        #OFFSET;
        forever
        begin
            CLK = 1'b1;
            #(PERIOD-(PERIOD*DUTY_CYCLE)) CLK = 1'b0;
            #(PERIOD*DUTY_CYCLE);
        end
    end 


    initial begin
        // Wait 100 ns for global reset to finish
        // Add stimulus here
        #200 ASM_SEL=1;
        #150 ASM_SEL=0;

    end


    integer h1;

    initial
    h1 = $fopen("AA2.dmp");//did not work as a seperate init/begin block..


    begin//No initial for $stobe
    always @ (posedge CLK)
    $monitor(h1,"    %d,    %b,    %b,    %h,    %h,    %b,    %b,    %b,    %h",
                h1,CLK, ASM_SEL,/* ADC_BUS,ADC_Wait_Time,*/ASM_HB,ASM_LB,
                AS_SConv, AS_OE, ASM_FLAG,
                S); end

    initial
    begin
  $display("ADC_SAMPLE_tb simulator output");
  $display ("h1,CLK, ASM_SEL,ASM_HB,ASM_LB,AS_SConv, AS_OE, ASM_FLAG,S");

    end
    initial
//  begin
    #2000 $fclose (h1);
//  end


endmodule

Answer 1

我认为您可能只需要使用

$fwrite代替$display
$fmonitor代替$monitor

$display和$monitor命令只是写入标准输出，但是$fwrite和$fmonitor可以让您将输出写入您自己的文件以h1打开。

Answer 2

附加了更新的测试平台。现在收到警告“文件/多通道描述符（2）传递给$ fclose无效”。 AA2.txt文件很有效。使用$ fwrite（而不是$ fmonitor）并且它有效，但有相同的警告。我应该忽略这个警告吗？我也尝试使用“reset”（SEE CODE）来开始/停止写入文件，但是复位始终是1，所以没有输出。你可以解释吗？ REPOSITN GMODIFIED CODE ..

``timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   16:57:34 12/04/2014
// Design Name:   ADC_SAMPLE
// Module Name:   C:/Xilinx131/SOC/SOC501V2/ADC_SAMPLE_tb.v
// Project Name:  SOC501V2
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: ADC_SAMPLE for review with Honeywell
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module ADC_SAMPLE_tb;

    // Inputs
    reg CLK;
    reg ASM_SEL;
    reg [11:0] ADC_BUS;
    reg [7:0] ADC_Wait_Time;

    // Outputs
    wire [7:0] ASM_HB;
    wire [7:0] ASM_LB;
    wire AS_SConv;
    wire AS_OE;
    wire ASM_FLAG;
    wire [3:0] S;

    parameter PERIOD = 100;
    parameter real DUTY_CYCLE = 0.5;
    parameter OFFSET = 0;


    // Instantiate the Unit Under Test (UUT)
    ADC_SAMPLE uut (
        .CLK(CLK), 
        .ASM_SEL(ASM_SEL), 
        .ADC_BUS(ADC_BUS), 
        .ADC_Wait_Time(ADC_Wait_Time), 
        .ASM_HB(ASM_HB), 
        .ASM_LB(ASM_LB), 
        .AS_SConv(AS_SConv), 
        .AS_OE(AS_OE), 
        .ASM_FLAG(ASM_FLAG), 
        .S(S)
    );

    initial begin
        // Initialize Inputs
        CLK = 0;
        ASM_SEL = 1;
        ADC_BUS = 12'hABC;
        ADC_Wait_Time = 4;
    end

   initial    
    begin
        #OFFSET;
        forever
        begin
            CLK = 1'b1;
            #(PERIOD-(PERIOD*DUTY_CYCLE)) CLK = 1'b0;
            #(PERIOD*DUTY_CYCLE);
        end
    end 


    initial begin
        // Wait 100 ns for global reset to finish
        // Add stimulus here
        #200 ASM_SEL=1;
        #150 ASM_SEL=0;

    end


    integer h1;
    reg reset;

    initial begin
    reset = 0;
    @(negedge ASM_FLAG) reset = 1;//at completion of sim, ASM_FLAG goes 0;
    end

    initial begin
    $display("ADC_SAMPLE_tb simulator output");
    $display ("h1,CLK, ASM_SEL,ASM_HB,ASM_LB,AS_SConv, AS_OE, ASM_FLAG,S");
    end

    initial begin
    h1 = $fopen("AA2.txt");//did not work as a seperate init/begin block..
    end



    always @ (posedge CLK)
    begin
    repeat (10)
//  while (reset == 0)
    begin
    $fwrite(h1,"%d,%b,%b,%b,%h,%h,%b,%b,%b,%h,\n",
                h1,reset,CLK, ASM_SEL,/* ADC_BUS,ADC_Wait_Time,*/ASM_HB,ASM_LB,
                AS_SConv, AS_OE, ASM_FLAG,
                S); 
    end
    $fclose (h1);

    end
endmodule

`

将verilog testbench输出保存到文件

2 个答案: