我想编写自己的测试平台,但它并没有给我输出。我尽我所能,但它没有帮助。任何人都可以帮我一把吗?
module direct(clk, reset, x, y);
input clk, reset;
input signed [7:0]x;
output signed [23:0]y;
reg signed [23:0]y;
reg signed [15:0]a[0:8]; //coeff
reg signed [7:0]rej[0:8]; //reg
reg signed [23:0]acc;
reg [4:0]count; //
always@(posedge clk)
begin: states
parameter s0=0, s1=1, s2=2, s3=3;
reg[1:0] state;
integer i;
if(reset == 0) begin
state <= s0;
end
else begin
case(state)
s0: begin
state <= s1;
acc <= 0;
a[0] <= 16'd887;
a[1] <= 16'd553;
a[2] <= -16'd2563;
a[3] <= -16'd8745;
a[4] <= 16'd19757;
a[5] <= -16'd8745;
a[6] <= -16'd2563;
a[7] <= 16'd553;
a[8] <= 16'd887;
for (i=0; i<9; i=i+1)
rej[i] <= 0;
end
s1: begin
state <= s2;
count <= 0;
acc <= 0;
rej[0]<= x;
for (i = 1; i <9; i=i+1)
rej[i] <= rej[i-1];
end
s2: begin
if(count ==9)
state <= s3;
else
begin
state <= s2;
count <= count + 1'd1;
acc <= acc + rej[count]*a[count];
end
end
s3: begin
state <= s1;
y <= acc;
end
default:state <=s0;
endcase
end
end
endmodule
我自己的测试平台:(如果有人能指出我做错了什么)
`timescale 1 ns / 100 ps
module direct_test();
reg clk, reset;
reg [7:0]x;
wire [23:0]y;
direct U1(
.clk(clk),
.reset(reset),
.x(x),
.y(y)
);
always
#10 clk = ~clk;
initial
begin
clk = 1'b0;
#5 reset <= 1'b0;
x <= 1'd1;
#10 reset <= 1'b1;
end
endmodule
答案 0 :(得分:0)
direct
模块中存在编译错误。变化:
for (i = 1; i <9; i=i+1) rejestry
为:
for (i = 1; i <9; i=i+1)
always
模块中的direct_test
块阻止模拟完成。将$finish
添加到initial
块:
initial
begin
clk = 1'b0;
#5 reset <= 1'b0;
x <= 1'd1;
#10 reset <= 1'b1;
#5000 $finish;
end
通过这些更改,我看到y
波形从X变为'h377,'h5a0等等。