Question

我为4位加法器编写了一个实体。此实体使用另一个1位全加器端口，如代码中所示：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;


entity adder4bit is
Port ( a,b : in  STD_LOGIC_VECTOR(3 downto 0);
       cin : in  STD_LOGIC;
       sum : out  STD_LOGIC_VECTOR(3 downto 0);
       cout : out  STD_LOGIC);
end adder4bit;

architecture Behavioral of adder4bit is

component FA is port(a,b,cin : in STD_LOGIC;
    sum,cout : out STD_LOGIC);
end component;
signal c : std_logic_vector(2 downto 0);

begin

fa0: FA port map(a(0),b(0),cin,sum(0),c(0));
fa1: FA port map(a(1),b(1),c(0),sum(1),c(1));
fa2: FA port map(a(2),b(2),c(1),sum(2),c(2));
fa3: FA port map(a(3),b(3),c(2),sum(3),cout);

end Behavioral;

然而，以下TestBench似乎并不像往常一样在波形中获得未初始化的值。我不确定Waveform的代码!!

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;


ENTITY adder4bit_TB IS
END adder4bit_TB;

ARCHITECTURE behavior OF adder4bit_TB IS 

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT adder4bit
PORT(
     a : IN  std_logic_vector(3 downto 0);
     b : IN  std_logic_vector(3 downto 0);
     cin : IN  std_logic;
     sum : OUT  std_logic_vector(3 downto 0);
     cout : OUT  std_logic
    );
END COMPONENT;




  --Inputs
   signal a : std_logic_vector(3 downto 0) := (others => '0');
   signal b : std_logic_vector(3 downto 0) := (others => '0');
   signal cin : std_logic := '0';

    --Outputs
   signal sum : std_logic_vector(3 downto 0);
   signal cout : std_logic;
   -- No clocks detected in port list. Replace <clock> below with 
   -- appropriate port name 

    --   constant <clock>_period : time := 10 ns;


BEGIN

-- Instantiate the Unit Under Test (UUT)
 uut: adder4bit PORT MAP (
      a => a,
      b => b,
      cin => cin,
      sum => sum,
      cout => cout
    );

 -- Clock process definitions
--   <clock>_process :process
--   begin
--      <clock> <= '0';
--      wait for <clock>_period/2;
--      <clock> <= '1';
--      wait for <clock>_period/2;
--   end process;




   -- Stimulus process
    stim_proc: process
    begin       
      -- hold reset state for 100 ns.
      wait for 100 ns;  

      a <= a + '1';
    end process;

   stim_proc1: process
   begin        
      -- hold reset state for 100 ns.
      wait for 50 ns;   

      b <= b + '1';
   end process;

   stim_proc2: process
   begin        
      -- hold reset state for 100 ns.
      wait for 25 ns;

      cin<=not cin;
   end process;

   END;

我想要实现的是分别以100和50 ns的间隔递增a和b。但在波形中，每个信号似乎都未初始化！我做错了什么？

编辑1： Adder4bit和FA的代码：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity FA is
    Port ( a,b,cin : in  STD_LOGIC;
           cout,sum : out  STD_LOGIC);
end FA;

architecture Behavioral of FA is
begin

    sum <= a xor b xor cin;
    cout <= (a and b) or (b and cin) or (cin and a);

end Behavioral;

Adder4bit：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity adder4bit is
    Port ( a,b : in  STD_LOGIC_VECTOR(3 downto 0);
           cin : in  STD_LOGIC;
           sum : out  STD_LOGIC_VECTOR(3 downto 0);
           cout : out  STD_LOGIC);
end adder4bit;

architecture Behavioral of adder4bit is

    component FA is port(a,b,cin : in STD_LOGIC;
        sum,cout : out STD_LOGIC);
    end component;
    signal c : std_logic_vector(2 downto 0);

begin

    fa0: FA port map(a(0),b(0),cin,sum(0),c(0));
    fa1: FA port map(a(1),b(1),c(0),sum(1),c(1));
    fa2: FA port map(a(2),b(2),c(1),sum(2),c(2));
    fa3: FA port map(a(3),b(3),c(2),sum(3),cout);

end Behavioral;

Answer 1

例如+ a + '1'未定义仅使用显示的包，因此为了快速入门，您可以添加：

use ieee.std_logic_unsigned.all;

使用非标准的Synopsys软件包。否则考虑：

use ieee.numeric_std.all;

用于标准包，需要稍加重写。

另外，检查编译警告/错误，因为这可能显示如下：

中缀运算符“+”没有可行条目。

Answer 2

我添加了一位全加法器的行为模型，并且之前已将您的测试平台转换为使用包numeric_std，因为Morten也表示：

library ieee;
use ieee.std_logic_1164.all;

entity FA is
    port (
        a,b,cin:    in  std_logic;
        sum, cout:  out std_logic
    );
end entity;

architecture foo of FA is
begin
    sum <= a xor b xor cin;
    cout <= (a and b) or (a and cin) or (b and cin);
end architecture;

library ieee;
use ieee.std_logic_1164.all;

entity adder4bit is
    port ( 
        a,b : in  std_logic_vector(3 downto 0);
        cin : in  std_logic;
        sum : out  std_logic_vector(3 downto 0);
        cout : out  std_logic
    );
end adder4bit;

architecture behavioral of adder4bit is

    component fa is 
        port ( 
            a,b,cin : in std_logic;
            sum,cout : out std_logic
        );
    end component;

    signal c : std_logic_vector(2 downto 0);

begin

fa0: fa port map(a(0),b(0),cin,sum(0),c(0));
fa1: fa port map(a(1),b(1),c(0),sum(1),c(1));
fa2: fa port map(a(2),b(2),c(1),sum(2),c(2));
fa3: fa port map(a(3),b(3),c(2),sum(3),cout);

end architecture behavioral;

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity adder4bit_tb is
end adder4bit_tb;

architecture behavior of adder4bit_tb is 

    component adder4bit
        port (
             a : in  std_logic_vector(3 downto 0);
             b : in  std_logic_vector(3 downto 0);
             cin : in  std_logic;
             sum : out  std_logic_vector(3 downto 0);
             cout : out  std_logic
        );
    end component;

--inputs
    signal a : std_logic_vector(3 downto 0) := (others => '0');
    signal b : std_logic_vector(3 downto 0) := (others => '0');
    signal cin : std_logic := '0';

--outputs
    signal sum : std_logic_vector(3 downto 0);
    signal cout : std_logic;

begin

uut: adder4bit 
    port map (
        a => a,
        b => b,
        cin => cin,
        sum => sum,
        cout => cout
    );

stim_proc: 
    process
    begin       
        wait for 100 ns;  

        a <= std_logic_vector(unsigned(a) + 1);
    end process;

stim_proc1: 
    process
    begin        
        wait for 50 ns;   

        b <= std_logic_vector(unsigned(b) + 1);
    end process;

stim_proc2: 
    process
    begin        
        wait for 25 ns;
        cin <= not cin;
    end process;

end architecture;

这产生了：

ghdl -a adder4bit.vhdl
  ghdl -e adder4bit_tb
  ghdl -r adder4bit_tb --stop-time = 1000ns --wave = adder4bit_tb.ghw
  ./adder4bit_tb:info：模拟停止--stop-time

（点击）

如您所见，波形中没有未初始化的值。

检查有关未绑定组件的消息，或者FA组件是否无法正常运行？

VHDL测试平台波形中的信号未初始化

2 个答案: