获取波形中的初始化值

时间:2018-03-08 09:41:14

标签: vhdl vivado

以下是测试平台

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity prime_tb is
end prime_tb;

architecture Behavioral of prime_tb is

   COMPONENT prime_tb
    PORT(
        clk     : in std_logic;  
        reset   : in std_logic;   
        seq_in  : in std_logic_vector(15 downto 0);     
        seq_out : out std_logic
  );
  END COMPONENT;

  signal reset   : std_logic := '0';
  signal clk     : std_logic := '0';
  signal seq_in  : std_logic_vector(15 downto 0);
  signal seq_out : std_logic;
  constant clk_period : time := 10 ns;

  begin

     uut: prime_tb PORT MAP (
        clk     => clk,
        reset   => reset,
        seq_in  => seq_in,
        seq_out => seq_out
     );

     clk_process :process
       begin
            clk <= '0';
            wait for clk_period/2;
            clk <= '1';
            wait for clk_period/2;
       end process;

     stim_proc: process
       begin   
           seq_in <=  "0000000011111111";             
               wait for clk_period;  
           seq_in <=  "0000000000001111";             
               wait for clk_period;                 
         wait;         
      end process;

end Behavioral;

我是VHDL的新手,我正在编写一个函数,它接受16位输入二进制值并确定它是否为素数。输出为&#39; 0&#39; 0或者&#39; 1&#39;(&#39; 1&#39;对于true,&#39; 0&#39;对于false)。但是当我运行模拟时,我得到的波形具有未初始化的值。似乎我的seq_in和seq_out都未初始化。见下面的链接。

错误:

enter image description here

有人可以帮我解决吗?

1 个答案:

答案 0 :(得分:2)

您的UUT实例化中存在拼写错误。你并不是这个意思:

   COMPONENT prime_tb
    PORT(
        clk     : in std_logic;  
        reset   : in std_logic;   
        seq_in  : in std_logic_vector(15 downto 0);     
        seq_out : out std_logic
  );
  END COMPONENT;

和此:

 uut: prime_tb PORT MAP (
    clk     => clk,
    reset   => reset,
    seq_in  => seq_in,
    seq_out => seq_out
 );

你的意思是:

   COMPONENT prime
    PORT(
        clk     : in std_logic;  
        reset   : in std_logic;   
        seq_in  : in std_logic_vector(15 downto 0);     
        seq_out : out std_logic
  );
  END COMPONENT;

和此:

 uut: prime PORT MAP (
    clk     => clk,
    reset   => reset,
    seq_in  => seq_in,
    seq_out => seq_out
 );

顺便说一句:你没有驱动UUT的重置输入。