Question

我正在尝试创建一个测试台文件来模拟我的添加/子模块，并且收到了以下两个错误：

错误：[USF-XSim-62]“精心制作”的步骤失败，并出现错误。请检查Tcl控制台输出以获取更多信息
错误：[Vivado 12-4473]运行模拟时检测到错误。请更正问题，然后重试此操作

我试图通过使用STD_LOGIC_VECTOR使我的代码看起来更好一些，并减少冗余。我想知道我是否实现不正确，还是我的VHDL代码有其他问题？

或者我的问题可能是在错误地声明我的实体？我首先用VHDL代码创建了一个完整的加法器，然后使用框图制作了我的添加/子模块。创建框图时，我必须应用包装器以设置约束。因此，我从未真正命名该实体，但“设计源”将其列出为“ AddSub_1_wrapper”，而展开后的框图名称为“ AddSub_1”。

“精致”文件包含以下内容：

Vivado Simulator 2018.2
Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved.
Running: C:/Xilinx/Vivado/2018.2/bin/unwrapped/win64.o/xelab.exe -wto 
53289afc3c364a2082c40394db3142eb --incr --debug typical --relax --mt 2 -L 
xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot 
testBench_lab2_behav xil_defaultlib.testBench_lab2 xil_defaultlib.glbl -log 
elaborate.log 
Using 2 slave threads.
Starting static elaboration
ERROR: [VRFC 10-923] index value <3> is out of range [2:0] of array <abc>
[C:/Users/jstev/Desktop/lab_2.1/lab_2.1.srcs/sim_1/new/addSub_TestBench.vhd:41] 
ERROR: [VRFC 10-923] index value <3> is out of range [2:0] of array <def>
[C:/Users/jstev/Desktop/lab_2.1/lab_2.1.srcs/sim_1/new/addSub_TestBench.vhd:42] 
ERROR: [XSIM 43-3322] Static elaboration of top level Verilog design unit(s) in library work failed.

注意：OP输入引脚变为1进行减法，为0进行加法。另外，添加/子模块在物理FPGA器件上的性能也达到了预期。

-----------------------------------------------------------------
-- Module Name: testBench_lab2
-- Target Devices: FPGA xc7a35tcpg236-1
-----------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity testBench_lab2 is
--  Port ( );
end testBench_lab2;

architecture Behavioral of testBench_lab2 is
    -- declare component teting --
    component AddSub_1_wrapper
       Port (A_0,A_1,A_2 : in STD_LOGIC;
             B_0,B_1,B_2 : in STD_LOGIC;
             OP: in STD_LOGIC;
             S_0,S_1,S_2 : out STD_LOGIC;
             Sign : out STD_LOGIC);
    end component;

    -- declare internal signals --
    signal abc : STD_LOGIC_VECTOR (2 downto 0);
    signal def : STD_LOGIC_VECTOR (2 downto 0);
    signal OP: STD_LOGIC := '0';
    signal S_0,S_1,S_2 : STD_LOGIC := '0';
    signal Sign: STD_LOGIC := '0';

begin
    UTT : AddSub_1_wrapper
        port map(A_0=>abc(3),A_1=>abc(2),A_2=>abc(3),
                 B_0=>def(3),B_1=>def(2),B_2=>def(3),
                 S_0=>S_0,S_1=>S_1,S_2=>S_0,
                 OP=>OP,Sign=>Sign);

    -- start testing process --
    process 
    begin
        -- add --
        wait for 30 ns;
        abc<="000"; def<="000"; wait for 10 ns; -- zero
        abc<="000"; def<="001"; wait for 10 ns; -- one
        abc<="001"; def<="001"; wait for 10 ns; -- one
        abc<="010"; def<="001"; wait for 10 ns; -- three
        abc<="011"; def<="001"; wait for 10 ns; -- four
        abc<="001"; def<="100"; wait for 10 ns; -- five
        abc<="100"; def<="010"; wait for 10 ns; -- six
        abc<="011"; def<="100"; wait for 10 ns; -- seven
        abc<="011"; def<="101"; wait for 20 ns; -- eight

        -- subtract --
        wait for 30 ns;  
        OP<='1';abc<="010"; def<="010"; wait for 10 ns; -- zero
        OP<='1';abc<="100"; def<="101"; wait for 10 ns; -- neg one
        OP<='1';abc<="001"; def<="011"; wait for 10 ns; -- neg two
        OP<='1';abc<="100"; def<="111"; wait for 10 ns; -- neg three 
        OP<='1';abc<="010"; def<="110"; wait for 10 ns; -- neg four
        OP<='1';abc<="001"; def<="110"; wait for 20 ns; -- neg five

    end process;
end Behavioral;

修复Vivado测试台添加/子错误（VHDL）？

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