vhdl altera数字时钟

时间:2017-12-14 14:05:55

标签: vhdl intel-fpga

我正在使用VHDL Altera板处理数字时钟。而且我在编码期间遇到了困难。我试图制作一个数字时钟,显示六个7段的小时,分​​钟和秒。我的代码是这样的:

 library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity time_main is
 port(clk_50mhz, reset, min_sw, hour_sw: in std_logic;     

   fnd_s: out std_logic_vector(5 downto 0);    
   fnd_d: out std_logic_vector(7 downto 0));   
end time_main;

architecture clock of time_main is

 signal clk_cnt: integer range 0 to 50000000;      
 signal data1, data3, data5, temp: integer range 0 to 9;   
 signal data2, data4: integer range 0 to 5;                
 signal data6: integer range 0 to 2;                       

 signal cnt: integer range 0 to 5;                         
 signal clk_test: integer range 0 to 5000000000; 

 variable decode_seg: std_logic_vector(7 downto 0);

  begin
   case count_seg is                    
   when 0 => decode_seg := "00111111";
   when 1 => decode_seg := "00000110";
   when 2 => decode_seg := "01011011";
   when 3 => decode_seg := "01001111";
   when 4 => decode_seg := "01100110";
   when 5 => decode_seg := "01101101";
   when 6 => decode_seg := "01111101";
   when 7 => decode_seg := "00100111";
   when 8 => decode_seg := "01111111";
   when 9 => decode_seg := "01101111";
   when others => decode_seg := "00000000";
  end case;
 return(decode_seg);       
end dis_7_seg;


 begin   

  process(clk_50mhz)
   begin
    if(clk_50mhz'event and clk_50mhz = '1') then                 
     if(clk_cnt = 50000000) then    
      clk_cnt <= 0;
     else
      clk_cnt <= clk_cnt + 1;
     end if;
    end if;
  end process;

  sec_1: process(clk_50mhz, reset)
   begin
    if(reset = '0') then      
     data1 <= 0;
    elsif(clk_50mhz'event and clk_50mhz = '1') then   
     if(clk_cnt = 50000000) then
      if(data1 = 9) then
       data1 <= 0;
      else
       data1 <= data1 + 1;
      end if;
     end if;
    end if;
  end process;

 sec_10: process(clk_50mhz, reset)
   begin
    if(reset = '0') then        
     data2 <= 0;
    elsif(clk_50mhz'event and clk_50mhz = '1') then         
     if(clk_cnt = 50000000) then
      if(data1 = 9) then
       if(data2 = 5) then
       data2 <= 0;
       else
       data2 <= data2 + 1;
      end if;
     end if;
    end if;
   end if;
  end process;

  min_1: process(clk_50mhz, reset)
   begin

    if(reset = '0') then          
     data3 <= 0;
    elsif(min_sw = '1') and (clk_50mhz'event and clk_50mhz = '1') then    
     if(clk_cnt = 50000000) then
      if(data3 = 9) then
       data3 <= 0;
      else
       data3 <= data3 + 1;
      end if;
     end if;                                                    
    elsif(clk_50mhz'event and clk_50mhz = '1') then         
     if(clk_cnt = 50000000) then
      if(data1 = 9 and data2 = 5) then
       if(data3 = 9) then
        data3 <= 0;
       else
        data3 <= data3 + 1;
       end if;
      end if;
     end if;
    end if;
   end process;

  min_10: process(clk_50mhz, reset)
   begin
    if(reset = '0') then       
     data4 <= 0;
    elsif(min_sw = '1') and (clk_50mhz'event and clk_50mhz = '1') then   
     if(clk_cnt = 50000000) then
      if(data3 = 9) then
       if(data4 = 5) then
        data4 <= 0;
       else
        data4 <= data4 + 1;
       end if;
      end if;
     end if;                                                    
     if(clk_cnt = 50000000) then
    elsif(clk_50mhz'event and clk_50mhz = '1') then                     
     if(clk_cnt = 50000000) then
      if(data1 = 9 and data2 = 5 and data3 = 9) then
       if(data4 = 5) then
        data4 <= 0;
       else
        data4 <= data4 + 1;
       end if;
      end if;
     end if;
    end if;
        end if;
  end process;

  hour_1: process(clk_50mhz, reset)
   begin
    if(reset = '0') then        
     data5 <= 0;
    elsif(hour_sw = '1') and (clk_50mhz'event and clk_50mhz = '1') then       
      if(clk_cnt = 50000000) then
      if(data5 = 3 and data6 = 2) then
       data5 <= 0;
      elsif(data5 = 9) then
       data5 <= 0;
      else
       data5 <= data5 + 1;
      end if;
     end if;                                                    
    elsif(clk_50mhz'event and clk_50mhz = '1') then        
     if(clk_cnt = 50000000) then
      if(data1 = 9 and data2 = 5 and data3 = 9 and data4 = 5) then
       if(data5 = 3 and data6 = 2) then
        data5 <= 0;
       elsif(data5 = 9)then
        data5 <= 0;
       else
        data5 <= data5 + 1;
       end if;
      end if;
     end if;
    end if;
   end process;

  hour_10: process(clk_50mhz, reset)
   begin
    if(reset = '0') then              
     data6 <= 0;
    elsif(hour_sw = '1') and (clk_50mhz'event and clk_50mhz = '1') then  
     if(clk_cnt = 50000000) then
      if(data5 = 3 and data6 = 2) then
       data6 <= 0;
      elsif(data5 = 9) then
       data6 <= data6 + 1;
      end if; 
     end if;                                                     
    elsif(clk_50mhz'event and clk_50mhz = '1') then     -
     if(clk_cnt = 50000000) then
      if(data1 = 9 and data2 = 5 and data3 = 9 and data4 = 5) then
       if(data5 = 3 and data6 = 2) then
        data6 <= 0;
       elsif(data5 = 9) then
        data6 <= data6 + 1;
       end if;
      end if;
     end if;
    end if;
   end process;

  process(clk_50mhz)
   begin
    if(clk_50mhz'event and clk_50mhz = '1') then                  
     if(clk_test = 5000000000) then    
      clk_test <= 0;
     else
      clk_test <= clk_test + 1;
     end if;
    end if;
  end process;

 process(clk_test)
   begin
    if(clk_test = 5000000000) then    
     if(cnt = 5) then
      cnt <= 0;
     else
     cnt <= cnt + 1;
    end if;
   end if;
 end process;

  process(data1, data2, data3, data4, data5, data6, cnt)
   begin

     If (cnt=0) then
      fnd_s <= "000001";  
      temp <= data1;
     else if(cnt=1) then
       fnd_s <= "000010";  
       temp <= data2;
     else if (cnt=2) then
       fnd_s <= "000100";  
       temp <= data3;
     else if (cnt=3) then 
       fnd_s <= "001000";  
       temp <= data4;
     else if (cnt=4) then
      fnd_s <= "010000";  
      temp <= data5;
     else if (cnt=5) then
      fnd_s <= "100000";  
      temp <= data6;     
     end if;
    end if;
   end if;
  end if;
  end if;
  end if;
   end process;


  fnd_d <= dis_7_seg(temp);  

  end clock;

=============================================== =========================

然而,我发现第一段没有显示任何东西,只是总OFF ...我发现其他5段显示相同的数字:从0到9持续9秒,然后段显示0再次,并从0到9继续计数。我以为我做了一个很好的代码,足以制作小时,分钟和秒......但它只显示了几秒钟......有人能告诉我我的代码有什么问题吗?拜托?

0 个答案:

没有答案