Question

我在做了一点Verilog之后开始尝试学习VHDL。

这是我尝试创建时钟分频器：（主要取自Making a clock divider）

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;

entity clock_192 is
    Port ( clk : in  STD_LOGIC;
           clr : in  STD_LOGIC;
           clk_out : out STD_LOGIC);
end clock_192;

architecture Behavioral of clock_192 is
signal q : std_logic_vector (23 downto 0);
begin
    clk_out <= q(23);
    process(clk,clr)
    begin
        if clr = '1' then
            q <= "000000000000000000000000";
        elsif clk'event and clk = '1' then
            q <= std_logic_vector(unsigned(q)+1);
        end if;
    end process;
end Behavioral;

这是我正在使用的测试台：

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;

ENTITY test_clock_192 IS
END test_clock_192;

ARCHITECTURE behavior OF test_clock_192 IS 

    -- Component Declaration for the Unit Under Test (UUT)

    COMPONENT clock_192
    PORT(
         clk : IN  std_logic;
         clr : IN  std_logic;
         clk_out : OUT  std_logic
        );
    END COMPONENT;


   --Inputs
   signal clk : std_logic := '0';
   signal clr : std_logic := '0';

    --Outputs
   signal clk_out : std_logic;

   -- Clock period definitions
   constant clk_period : time := 10 ns;
   constant clk_out_period : time := 10 ns;

BEGIN

    -- Instantiate the Unit Under Test (UUT)
   uut: clock_192 PORT MAP (
          clk => clk,
          clr => clr,
          clk_out => clk_out
        );

   -- Clock process definitions
   clk_process :process
   begin
        clk <= '0';
        wait for clk_period/2;
        clk <= '1';
        wait for clk_period/2;
   end process;

   clk_out_process :process
   begin
        clk_out <= '0';
        wait for clk_out_period/2;
        clk_out <= '1';
        wait for clk_out_period/2;
   end process;


   -- Stimulus process
   stim_proc: process
   begin        
      -- hold reset state for 100 ns.
        clr <= '1';
      wait for 97 ns;   
        clr <= '0';

      wait for clk_period*10;

      -- insert stimulus here 

      wait;
   end process;

END;

问题是我的clk_out信号在clk的每个循环中一直在0和X之间翻转。如下所示：

有没有人知道发生了什么？

编辑：为了解决这个问题，我不得不改变我的测试平台，看起来像这样：

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;

ENTITY test_clock_192 IS
END test_clock_192;

ARCHITECTURE behavior OF test_clock_192 IS 

    -- Component Declaration for the Unit Under Test (UUT)

    COMPONENT clock_192
    PORT(
         clk : IN  std_logic;
         clr : IN  std_logic;
         clk_out : OUT  std_logic
        );
    END COMPONENT;


   --Inputs
   signal clk : std_logic := '0';
   signal clr : std_logic := '0';

    --Outputs
   signal clk_out : std_logic;

   -- Clock period definitions
   constant clk_period : time := 10 ns;
   constant clk_out_period : time := 10 ns;

BEGIN

    -- Instantiate the Unit Under Test (UUT)
   uut: clock_192 PORT MAP (
          clk => clk,
          clr => clr,
          clk_out => clk_out
        );

   -- Clock process definitions
   clk_process :process
   begin
        clk <= '0';
        wait for clk_period/2;
        clk <= '1';
        wait for clk_period/2;
   end process;

   -- Stimulus process
   stim_proc: process
   begin        
      -- hold reset state for 100 ns.
        clr <= '1';
      wait for 97 ns;   
        clr <= '0';

      wait for clk_period*10;

      -- insert stimulus here 

      wait;
   end process;

END;

Answer 1

测试平台从saveWithBlockAndWait实例和clk_out进程驱动uut信号，这使得clk_out_process的解析功能生效。

如果两个来源都为std_logic，那么生成的'0'值将为clk_out，但如果一个来源驱动'0'而另一个来自'0'，则正如您所见，分辨率函数将返回'1'。

您可以查看here以获取有关“VHDL解析功能”的一些说明，或尝试谷歌搜索。

VHDL时钟分频器在每个clk周期内翻转0到X.

1 个答案: