Question

这是fir过滤器的vhdl代码：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;

entity FIR is

 port(

        CLK2: in std_logic;

          Sendin : in std_logic;          
          Sendout: out std_logic;

        Din : in std_logic_vector(11 downto 0);
          Dout: out std_logic_vector(11 downto 0)
    );
end FIR;

architecture Behavioral of FIR is

signal count : std_logic_vector(5 downto 0) := "000000";
signal send : std_logic := '0';
signal Dout_S : std_logic_vector(11 downto 0) := x"000";

type multype is array(36 downto 0) of std_logic_vector(23 downto 0);
signal mult : multype :=  ((others=> (others=>'0')));
type addtype is array(36 downto 0) of std_logic_vector(11 downto 0);
signal adder : addtype :=((others=> (others=>'0')));

type reg is array(36 downto 0) of std_logic_vector(11 downto 0);
signal shiftreg : reg:=  ((others=> (others=>'0')));

signal coefs : reg:= (
 x"015",x"02F",x"05E",x"0A8",x"114",x"1A8",x"268",x"356",x"472"
,x"5B6",x"71B",x"894",x"A10",x"B7E",x"CCC",x"DE6",x"EBD",x"F43"
,x"F71",x"F43",x"EBD",x"DE6",x"CCC",x"B7E",x"A10",x"894",x"71B"
,x"5B6",x"472",x"356",x"268",x"1A8",x"114",x"0A8",x"05E",x"02F"
,x"015"
);

begin

FIRcal:process(ClK2,Sendin) 
begin

if rising_edge(clk2) then
count<=count + 1;
if Sendin = '1' then
      shiftreg<=shiftreg(35 downto 0) & Din;

for I in 36 downto 0 loop
MULT(I) <= shiftreg(36-I) * COEFS(36-I);

if I = 0 then
ADDER(I) <= x"000" + ("000000" & MULT(I)(23 downto 17));
else
ADDER(I) <= ("000000" & MULT(I)(23 downto 17)) + ADDER(I-1);
end if;
end loop;

DOUT_S <= ADDER(36);
send <='1';

end if;
end if;
end process FIRcal;

--FIRsend: process(ClK2,Send) 
--begin

--if rising_edge(clk2) then
--if send <= '1' then
--   send <='0';
--end if;
--end if;
--end process FIRsend;

Sendout <= Send;
Dout <= Dout_S;

end Behavioral;

测试平台

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;


ENTITY fvfv IS
END fvfv;

ARCHITECTURE behavior OF fvfv IS 


    COMPONENT FIR
    PORT(
         CLK2 : IN  std_logic;
         Sendin : IN  std_logic;
         Sendout : OUT  std_logic;
         Din : IN  std_logic_vector(11 downto 0);
         Dout : OUT  std_logic_vector(11 downto 0)
        );
    END COMPONENT;


   --Inputs
   signal CLK2 : std_logic := '0';
   signal Sendin : std_logic := '0';
   signal Din : std_logic_vector(11 downto 0) := (others => '0');

    --Outputs
   signal Sendout : std_logic;
   signal Dout : std_logic_vector(11 downto 0);

   -- Clock period definitions
   constant CLK2_period : time := 10 ns;

BEGIN

    -- Instantiate the Unit Under Test (UUT)
   uut: FIR PORT MAP (
          CLK2 => CLK2,
          Sendin => Sendin,
          Sendout => Sendout,
          Din => Din,
          Dout => Dout
        );

   -- Clock process definitions
   CLK2_process :process
   begin
        CLK2 <= '0';
        wait for CLK2_period/2;
        CLK2 <= '1';
        wait for CLK2_period/2;
   end process;


   -- Stimulus process
   stim_proc: process
   begin
     Din <= x"0F0";     
      wait for 10 ns;
     sendin<='1';
     wait for 10 ns;
     sendin<='0';     
     wait for 300 ns; 
      Din <= x"090";
      sendin<='1';
      wait for 10 ns;
      sendin<='0'; 
   end process;

END;

enter image description here

测试平台仅显示三个clk周期，我尝试延长时间，但它没有工作，我的代码有问题吗？

Answer 1

以下行中有错误：

 if I = 0 then
     ADDER(I) <= x"000" + ("00000" & MULT(I)(23 downto 17));
 else
     ADDER(I) <= ("00000" & MULT(I)(23 downto 17)) + ADDER(I-1);
 end if;

正如我在评论中所说，你有不同大小的矢量。

要解决此问题，您需要等同尺寸取决于您的逻辑（从右侧删除一个0或展开ADDER元素：

 if I = 0 then
     ADDER(I) <= x"000" + ("0000" & MULT(I)(23 downto 17));
 else
     ADDER(I) <= ("0000" & MULT(I)(23 downto 17)) + ADDER(I-1);
 end if;

OR

type addtype is array(36 downto 0) of std_logic_vector(12 downto 0);
signal adder : addtype :=((others=> (others=>'0')));

VHDL Testbench仿真仅显示三个clk循环

1 个答案: