TG68核心clk，重置，堆栈

Question

这是代码的一部分，我不知道如何设置clk，reset和dtack关系，因为没有它，TG68核心将无法启动。此代码还需要进行一些修改，但让我们从小处着手。有谁能提出建议？

TG68_inst: TG68
PORT MAP (
    data_in           => ioTG68_DATA,       
      data_out          => data_out,
      clk               => clk_7MHz, -- 7Mhz clk
      reset             => tg68_reset,
      clkena_in         => '1',
      IPL               => iTG68_IPLn,
      dtack             => iTG68_DTACKn,
      addr(31 downto 24) => open,
      addr(23 downto 1) => oTG68_ADDR,
      addr(0)             => open,
      as                => as,
      rw                => rw,
      uds               => uds,
      lds               => lds
    );


data_oe <= (not as) and (not rw) and (not uds);

-- Tri-state bus
ioTG68_DATA <= (others => 'Z') when (data_oe = '0') else data_out;