输出只是一个clk周期而不是三个

时间:2016-03-07 07:07:11

标签: verilog

我写了这段代码。当输入B为1时输出必须为3 clk周期,但当我尝试测试时,输出仅为一个clk周期。我不知道如何更改代码以获得欲望输出。

module LaserTimerTopDown (

B,X,Clk,Rst);

    input B;

    output reg X;

    input Clk,Rst;

    parameter S_OFF =0, S_ON=1;

    // shared variable

    reg Cnt_Sel, Cnt_Eq_0, Cnt_Ld;

    // datapath variable

    reg [1:0] Cnt, CntNext;

    // controller variable

    reg [0:0] State, StateNext;

    // Datapath Procedures

    always @(Cnt, Cnt_Sel) begin

        if (Cnt_Sel == 1)

            CntNext <= 2'b10;

        else

            CntNext <= Cnt -1;

        Cnt_Eq_0 <= (Cnt ==0)? 1:0;
    end

    always @ (posedge Clk) begin
        if (Rst ==1)
            Cnt <= 0;
        else if (Cnt_Ld ==1)
            CntNext <= Cnt;
    end
    // Controler Procedures 
    always @(Cnt_Eq_0, B, State)begin
        case(State)
            S_OFF :begin
                X<= 0; Cnt_Sel <= 1; Cnt_Ld <= 1;
                if (B==0)
                    StateNext <= S_OFF;
                else
                    StateNext <= S_ON;
             end
             S_ON : begin
                X<= 1; Cnt_Sel <= 0; Cnt_Ld <= 1;
                if(Cnt_Eq_0 ==0)
                    StateNext <= S_ON;
                else
                    StateNext <= S_OFF;
              end  
        endcase
    end
    always @(posedge Clk) begin
        if (Rst ==1)
            State <= S_OFF;
        else
            State<= StateNext;
    end
endmodule

1 个答案:

答案 0 :(得分:0)

class Foo(object):

      def __init__(self):
        self._bar = 0

      @property
      def Bar(self):
        return self._bar

      @Bar.setter
      def Bar(self, value):
        self._bar = value


foo = Foo()
print(foo.Bar)  # called Bar getter
foo.Bar = 10  # called Bar setter
print(foo.Bar)  # called Bar getter