heloo我目前在ALTERA DE2开发板上工作。我要使用液晶显示屏。我强迫打开它。在此代码中,如果编号为1的代码为:“ 0100110001”,则lcd_bus是excdle的lcd的输出。 所以如果我写代码: 当1 => lcd_bus <=“ 0100110001”时,我将看到输出lcd_bus = 0100110001。这是此示例的代码:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY lcd_user_logic IS
GENERIC (display_resolution : INTEGER :=23; -- counter to get to the lowest ferquncy
display_counter: INTEGER :=8); -- counter to get to 97KHz ferquincy
PORT(
lcd_bus_ones : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
--COUNTER_VECTOR :IN STD_LOGIC_VECTOR(display_counter downto 0);
lcd_busy : IN STD_LOGIC; --lcd controller busy/idle feedback
clk : IN STD_LOGIC; --system clock
lcd_clk : OUT STD_LOGIC;
reset_n : OUT STD_LOGIC;
lcd_enable : buffer STD_LOGIC; --lcd enable received from lcd controller
lcd_bus : BUFFER STD_LOGIC_VECTOR(9 DOWNTO 0)); --data andcontrol signals
--The MSB is the rs signal, followed by the rw signal.
-- The other 8 bits are the data bits.
END lcd_user_logic;
ARCHITECTURE behavior OF lcd_user_logic IS
signal lcd_bus_ones_signal : STD_LOGIC_VECTOR(display_counter+1 downto 0);
BEGIN
lcd_bus_ones_signal<=lcd_bus_ones;
PROCESS(clk,lcd_bus_ones,lcd_bus_ones_signal)
VARIABLE char : INTEGER RANGE 0 TO 12 := 0;
BEGIN
IF(clk'EVENT AND clk = '1') THEN
IF(lcd_busy = '0' AND lcd_enable = '0') THEN
-- lcd_bus <= lcd_bus_ones;
lcd_enable <= '1';
IF(char < 12) THEN
char := char + 1;
END IF;
CASE char IS
---------------------------------------------------------------------------this is the test
WHEN 1 => lcd_bus <="1000110001";
WHEN OTHERS => lcd_enable <= '0';
END CASE;
ELSE
lcd_enable <= '0';
END IF;
END IF;
END PROCESS;
reset_n <= '1';
lcd_clk <= clk;
END behavior;
,输出实际上将是lcd_bus <=“ 1000110001” enter image description here
如果例如我想为lcd_bus输入一个值,lcd_bus <= lcd_bus_ones,那么我会得到lcd_bus =“ 0000000000” 代码看起来像这样:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY lcd_user_logic IS
GENERIC (display_resolution : INTEGER :=23; -- counter to get to the lowest ferquncy
display_counter: INTEGER :=8); -- counter to get to 97KHz ferquincy
PORT(
lcd_bus_ones : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
--COUNTER_VECTOR :IN STD_LOGIC_VECTOR(display_counter downto 0);
lcd_busy : IN STD_LOGIC; --lcd controller busy/idle feedback
clk : IN STD_LOGIC; --system clock
lcd_clk : OUT STD_LOGIC;
reset_n : OUT STD_LOGIC;
lcd_enable : buffer STD_LOGIC; --lcd enable received from lcd controller
lcd_bus : BUFFER STD_LOGIC_VECTOR(9 DOWNTO 0)); --data andcontrol signals
--The MSB is the rs signal, followed by the rw signal.
-- The other 8 bits are the data bits.
END lcd_user_logic;
ARCHITECTURE behavior OF lcd_user_logic IS
signal lcd_bus_ones_signal : STD_LOGIC_VECTOR(display_counter+1 downto 0);
BEGIN
lcd_bus_ones_signal<=lcd_bus_ones;
PROCESS(clk,lcd_bus_ones,lcd_bus_ones_signal)
VARIABLE char : INTEGER RANGE 0 TO 12 := 0;
BEGIN
IF(clk'EVENT AND clk = '1') THEN
IF(lcd_busy = '0' AND lcd_enable = '0') THEN
-- lcd_bus <= lcd_bus_ones;
lcd_enable <= '1';
IF(char < 12) THEN
char := char + 1;
END IF;
CASE char IS
---------------------------------------------------------------------------this is the test
WHEN 1 => lcd_bus <=lcd_bus_ones;
WHEN OTHERS => lcd_enable <= '0';
END CASE;
ELSE
lcd_enable <= '0';
END IF;
END IF;
END PROCESS;
reset_n <= '1';
lcd_clk <= clk;
END behavior;
所以输出结果应该是这样
问题出在这个陈述上:
IF(lcd_busy ='0'并且lcd_enable ='0')然后
有人知道如何解决此问题吗?
答案 0 :(得分:0)
对不起,信誉不足,无法发表评论。
仅通过波形显示中显示的2或3个信号就很难确定发生了什么。请至少将lcd_busy
和lcd_enable
添加到波形中。看来您的lcd_busy
信号可能设置为非0的值。我已经模拟了代码,对lcd_bus_ones
信号的分配对我来说很好。
此外,如果可能的话,很高兴看到该实体外部发生了什么事情。
您要char
停在12点吗?除非您提供一种重置char
的方法,否则现在定义的方式将达到12,并且有问题的分配不会再发生。