Question

我试图在verilog中制作循环计数器

module rr_arbiter (
clk, // positive edge trigger
reset,  // negative edge trigger
req0, req1, req2, req3, 
grant0, grant1, grant2, grant3,
priority, priority_req);

input clk, reset;
input req0, req1, req2, req3;
input priority;
input [1:0] priority_req;

output grant0, grant1, grant2, grant3;  

reg x 

always(posedge clk or negedge reset) begin
pirority_req = priority;

if (reset) begin
    grant0 <= 1'b0;
    grant1 <= 1'b0;
    grant2 <= 1'b0;
    grant3 <= 1'b0;
   end
else
begin
    if(priority == 1)
        if (priority req == 2b'00)
            begin
            x=1;
            grant0 <= (grant0*(~x))+(grant1*x);     
            x=0;
            grant0 <= (grant0*(~x))+(grant1*x);
            grant1 <= grant2;
            grant2 <= grant3;
            grant3 <= grant1;
            //  counter 0012300123
            end
        else if (priority req == 2b'01)
            begin
            grant0 <= grant1;
            x=1;
            grant1 <= (grant1*(~x))+(grant2*x);
            x=0;
            grant1 <= (grant1*(~x))+(grant2*x);
            grant2 <= grant3;
            grant3 <= grant1;
            //  counter 0112301123
            end
        else if (priority req == 2b'10)
            begin
            grant0 <= grant1;
            grant1 <= grant2;
            x=1;
            grant2 <= (grant2*(~x))+(grant3*x);
            x=0;
            grant2 <= (grant2*(~x))+(grant3*x);
            grant3 <= grant1;
            //  counter 0122301223
            end
        else if (priority req == 2b'11)
            begin
            grant0 <= grant1;
            grant1 <= grant2;
            grant2 <= grant3;
            x=1;
            grant3 <= (grant3*(~x))+(grant1*x);
            x=0;
            grant3 <= (grant3*(~x))+(grant1*x);
            //  counter 0123301233
            end
    end

    else 
    begin
        grant0 <= ~grant2 * grant3;
        grant1 <= grant0;
        grant2 <= grant1;
        grant3 <= grant2;
        //counter 01230123
    end
end
end

end

endmodule

正如你所看到的，我正试图制作循环计数器。每个案例都像（授予）01230123 ..，0012300123 ..，0112301123 ..，0122301223 ..，0123301233 ...

**错误：（vlog-13069）C：/Modeltech_pe_edu_10.4a/examples/rr_arbiter.v(17）：near＆＃34; always＆＃34 ;:语法错误，意外总是，期待＆＃39 ;; ＆＃39;或＆＃39;，＆＃39;。

**错误：（vlog-13069）C：/Modeltech_pe_edu_10.4a/examples/rr_arbiter.v(22）：near＆＃34;＆lt; =＆＃34 ;:语法错误，意外＆lt; =。< / p>
**错误：C：/Modeltech_pe_edu_10.4a/examples/rr_arbiter.v（22）:( vlog-13205）在＆＃39; grant0＆＃39;之后的范围内发现语法错误。是否缺少＆＃39; ::＆＃39;？

Answer 1

第17行的错误消息不言自明。它期待一个＆＃39 ;;＆＃39;。你错过了一个＆＃39 ;;＆＃39;在第15行。

如果显示错误消息没有任何意义，请始终注意屏幕以查看问题是否与上一行有关。

在verilog中制作计数器，Modelsim

1 个答案: