Question

我在verilog中编写了乘法器，得到两个32位操作数并返回64位输出。我测试了这个代码为5位它正常工作，但是当我运行此代码时，什么都不会发生，我也无法停止或结束模拟ModelSim。你对这个问题有任何想法吗？

    module multiplier_always(operand1,operand2,product);
input [31:0] operand1 ,operand2;
output reg [63:0] product; 

reg [63:0] op1;
reg [31:0] op2,addres,subres;
reg [64:0] subres2,result,addres2,opp1;
reg [2:0] i=0;



always@(*)
begin
        op1 = {32'b0,operand1};
        opp1 = {op1,1'b0};

for(i=0;i<32;i=i+1)
begin
case(opp1[1:0])
2'b00:begin
            opp1 = {opp1[64],opp1[64:1]};
            end

2'b01:begin
                addres = opp1[64:6]+ operand2; 
                addres2 = {addres,opp1[32:0]}; 
                opp1 = {addres2[64],addres2[64:1]}; 
            end

2'b10:begin 
                subres = opp1[64:6]+ (~operand2+1);
                subres2 = {subres,opp1[32:0]}; 
                opp1 = {subres2[64],subres2[64:1]};
            end

2'b11:begin
            opp1 = {opp1[64],opp1[64:1]};//shift
            end

endcase
end
product = opp1[64:1];

end
endmodule

Answer 1

reg [2:0] i的无限循环总是小于32;在i+1时，0为i==7。更改为integer i或reg [5:0] i。

在verilog中乘以两个32位操作数

1 个答案: