Question

我曾尝试在Verilog中编写代码，使用32位进位前瞻加法器将两个32位二进制数相乘，但我的程序无法编译。对于零件'if（store [0] == 1）'和'if（C [32] == 1）'

，Modelsim继续出现the generate if condition must be a constant expression错误

这是我遵循的算法：

Begin Program
Multiplier = 32 bits
Multiplicand = 32 bits
Register = 64 bits
Put the multiplier in the least significant half and clear
the most significant half
For i = 1 to 32
Begin Loop
If the least significant bit of the 64-bit register
contains binary ‘1’
Begin If
Add the Multiplicand to the Most Significant
Half using the CLAA
Begin Adder
C[0 ] = ’0’
For j = 0 to 31
Begin Loop
Calculate Propagate P[j] = Multiplicand[j]^ Most Significant Half[j]
Calculate Generate G[j] =
Multiplicand[j]·Most Significant Half[j]
Calculate Carries C[i + 1] = G[i] + P[i] ·
C[i]
Calculate Sum S[i] = P[i] Å C[i]
End Loop
End Adder
Shift the 64-bit Register one bit to the right 
throwing away the least significant bit
Else
Only Shift the 64-bit Register one bit to the
right throwing away the least significant bit
End If
End Loop
Register = Sum of Partial Products
End Program

代码：

module Multiplier_32(multiplier,multiplicand,store);
  output store;
  input [31:0]multiplier,multiplicand;
  wire [63:0]store;
  genvar i,j;
  wire g=32;
  wire [31:0]P,G,sum;
  wire [32:0]C;
  assign store[31:0]=multiplier;

  generate for(i=0;i<32;i=i+1)
  begin
    if(store[0]==1)
    begin
      assign C[0]=0;
      for(j=0;j<32;j=j+1)
      begin
        assign P[j]= multiplicand[j]^store[g];
        assign  G[j]=multiplicand[j]&store[g];
        assign  C[j+1]=G[i]|(P[i]&C[j]);
        assign  sum[j]=P[i]^C[j];
        assign g=g-1;
      end

      assign store[63:32]=sum[31:0];

      if(C[32]==1)
      begin
        assign store[62:0]=store[63:1];
        assign store[63]=1;
      end
      else 
      begin
        assign store[62:0]=store[63:1];
        assign store[63]=0;
      end
    end
    else
    begin
      assign store[62:0]=store[63:1];
      assign store[63]=0;    
    end
  end
endgenerate 
endmodule

Answer 1

在编译/精化时评估generate块。它们用于从模式构造硬件而不用于评估逻辑。目前尚不知道store[0]，C[32]和所有其他信号的值。唯一知道的值是参数和genvars。

在这种情况下，组合块（always @*）将满足您的功能要求。将所有wire替换为reg，但always @*内的所有作业，以及删除所有assign个关键字assign都不应在always内使用{1}}阻止）。

module Multiplier_32(
    input [31:0] multiplier, multiplicand,
    output reg [63:0] store
  );

integer i,j;
integer g;
reg [31:0] P,G,sum;
reg [32:0] C;

always @* begin
  g = 32;
  store[31:0]=multiplier;
  for(i=0;i<32;i=i+1) begin
    // your code here, do not use 'assign'
  end
end
endmodule

使用32位进位超前加法器将两个32位数相乘

1 个答案: