Question

您好我想实现128位分层进位前瞻加法器，但我不知道如何在我的实现中使用级别，实际上我不知道如何编写代码。我为16位加法器编写代码，但我应该使用4位块并将它们组合在一起。我几乎知道在1级需要32位4位块，在2级需要8位数，依此类推。但是我的代码应该运行128到256位操作数，但我不知道如何执行此操作。请帮帮我

Answer 1

如果您已经有4位加法器，则应该实现分层加法器 with for generate语句如下：

    library ieee;
    use ieee.std_logic_1164.all;

    entity carry_leveled is
        generic(c_word_length : integer := 128;
                c_adder_count : integer := c_word_length / 4 --count of adder entities to generate
        );
        port(
            clk_i : in  std_logic;
            rst_i : in  std_logic;
            x_i   : in  std_logic_vector(c_word_length - 1 downto 0);
            y_i   : in  std_logic_vector(c_word_length - 1 downto 0);
            sum_o : out std_logic_vector(c_word_length - 1 downto 0)
        );
    end entity carry_leveled;

    architecture RTL of carry_leveled is
        component carry_lookahead_adder
            port(
                clk_i     : in  std_logic;
                rst_i     : in  std_logic;
                x_i       : in  std_logic_vector(c_word_length - 1 downto 0);
                y_i       : in  std_logic_vector(c_word_length - 1 downto 0);
                carry_i   : in  std_logic;
                carry_out : out std_logic;
                sum_o     : out std_logic_vector(3 downto 0)
            );
        end component;
        signal carry_vector : std_logic_vector(c_adder_count - 1 downto 0);
        signal sum          : std_logic_vector(c_word_length - 1 downto 0);
    begin

        sum_o <= sum;

        carry_lookahead_adder_inst_0 : component carry_lookahead_adder
            port map(clk_i     => clk_i,
                     rst_i     => rst_i,
                     x_i       => x_i(c_adder_count - 1 downto 0),
                     y_i       => y_i(c_adder_count - 1 downto 0),
                     carry_i   => '0',
                     carry_out => carry_vector(0),
                     sum_o     => sum(c_adder_count - 1 downto 0));

        carry_look_adder_generate : for i in 1 to c_adder_count - 1 generate
            carry_lookahead_adder_inst_i : component carry_lookahead_adder
                port map(clk_i     => clk_i,
                         rst_i     => rst_i,
                         x_i       => x_i((i + 1) * c_adder_count - 1 downto i * c_adder_count),
                         y_i       => y_i((i + 1) * c_adder_count - 1 downto i * c_adder_count),
                         carry_i   => carry_vector(i - 1),
                         carry_out => carry_vector(i),
                         sum_o     => sum((i + 1) * c_adder_count - 1 downto i * c_adder_count)
                );
        end generate carry_look_adder_generate;

    end architecture RTL;

希望我能帮助你

VHDL中的128位分层进位前瞻加法器

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