我正在设计一个8位序列检测器。但是下面的代码在modelsim
中编译时给出了错误- 编译模块SEQDET **错误:F:\ Modeltech_pe_edu_10.4a \ examples \ avlsihw5.v(30):找到一个空体的开始/结束块。这在SystemVerilog中是允许的,但在Verilog中是不允许的。请查找任何流浪的分号。 **错误:(vlog-13069)**解析宏扩展时:'A'从F开始:\ Modeltech_pe_edu_10.4a \ examples \ avlsihw5.v(43) **在F:\ Modeltech_pe_edu_10.4a \ examples \ avlsihw5.v(43):near“;”:语法错误,意外';',期待':'。
**错误:F:\ Modeltech_pe_edu_10.4a \ examples \ avlsihw5.v(46):( vlog-13205)在'shiftReg'后面的范围内发现语法错误。是否缺少'::'?
Verilog代码:
module seq_det;
wire SEQ_DETECTED;
reg [0:7] latch;
wire RST_N, SCK;
reg SCK,SDI;
SEQDET s1(SEQ_DETECTED,latch,RST_N,SDI,SCK);
clkGen #(10) cg(SCK);
//TEST at(latch,RST_N,SDI,SEQ_DETECTED,SCK);
endmodule
module SEQDET(.SEQ_DETECTED(SEQ_DETECTED),.latch(PATTERN),.RST_N(RST_N),.SDI(SDI),.SCK(SCK));
`define A 3'b000;
`define B 3'b001;
`define C 3'b100;
reg [7:0] shiftReg;
output SEQ_DETECTED;
input PATTERN;
input RST_N, SDI, SCK;
wire SEQ_DETECTED;
reg [2:0] state;
reg RST_N, SDI;
integer count, match;
initial begin
match = 0;
count = 0;
shiftReg = 8'b00000000;
RST_N = 1;
SEQ_DETECTED = 0;
state = `A;
end
always @(negedge RST_N) begin
PATTERN = {8{1'b0}};
SEQ_DETECTED = 0;
count = 0;
match = 0;
end
always @(posedge SCK)
if ( SCK && RST_N)
case (state)
`A : //begin
while(count <= 8) begin
shiftReg <= shiftReg | SDI ;
shiftReg = shiftReg >> 1;
count = count + 1;
if(count === 8)
if(shiftReg === PATTERN)
match = 1;
else
match = 0;
else ; end
state <= match ? `B : `C ;
//end
`B : //begin
count = 0;
match = 0;
shiftReg = {8{1'b0}};
SEQ_DETECTED = 1;
#20 SEQ_DETECTED = 0;
state <= `A ;
//end
`C : //begin
count = 0;
match = 0;
shiftReg = {8{1'b0}};
state <= `A ;
//end
endcase
endmodule
module clkGen(SCK);
output SCK;
parameter period = 10;
reg SCK;
initial SCK = 0;
always
#(period/2) SCK = ~SCK;
endmodule
答案 0 :(得分:1)
错误,
1.您不能声明两个具有相同名称的变量,即wire和reg CLK
2.无需绑定或连接实例化模块,即模块SEQDET(.SEQ_DETECTED(SEQ_DETECTED),. latch(PATTERN),. RST_N(RST_N),. SDI(SDI),。SCK(SCK));
3.连接模块通过线连接,因此不能与reg连接,它应该是输入线RST_N,SDI,SCK;只有
4.在case语句中,语法错误如,else;结束,应该是
if(count === 8)
if(shiftReg === PATTERN)
match = 1;
else
match = 0;
else
end
state <= match ? B : C ;
答案 1 :(得分:0)
然后,您获得的错误可能与`define
语句后的分号有关。 `define
作为字面替换。当你说
case (state)
`A : begin // <-- appears legal syntax
...
你得到:
case (state)
3'b000; : begin // <-- illegal syntax
...
将`define A 3'b000;
更改为`define A 3'b000
,然后您将获得正确的语法。
您正在以不寻常的方式执行模块标头。端口以.port_identifier(port_expression)
声明的模块在技术上是合法的,但在标头中很少使用;它通常在将网络连接到模块实例时使用。大多数人只用port_expression
写入非ANSI样式的模块头端口,丢弃.port_identifier()
。我建议使用ANSI样式标题(除非您需要遵循严格的1995编码样式)。
module SEQDET(.SEQ_DETECTED(SEQ_DETECTED),.latch(PATTERN),.RST_N(RST_N),.SDI(SDI),.SCK(SCK));
`define A 3'b000; // <---do not use semicolons here
`define B 3'b001; // <-+ here
`define C 3'b100; // <-+ and here
reg [7:0] shiftReg;
output SEQ_DETECTED;
input PATTERN; // <-- Are you sure you want this as a single bit?
input RST_N, SDI, SCK;
wire SEQ_DETECTED;
reg [2:0] state;
reg RST_N, SDI;
integer count, match;
写得更好:
module SEQDET(
output reg SEQ_DETECTED, // <-- based on ussage, this needs to be an reg type
input [7:0] PATTERN, // <-- I'm guessing you meant 8-bits
input RST_N, SDI,SCK
);
`define A 3'b000
`define B 3'b001
`define C 3'b100
reg [7:0] shiftReg;
reg [2:0] state;
integer count, match;
要合成always @(negedge RST_N)
和always @(posedge SCK)
需要合并为一个always @(posedge SCK or negedge RST_N)
强烈建议在分配触发器时使用非阻塞分配(<=
)。
延迟(例如:#20
)不是综合性的。你应该创建一个额外的状态。